Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2017.12.15
Emulated RSDS_E_1R Transmitter Timing Specifications
Table 39. Emulated RSDS_E_1R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
Emulated RSDS_E_1R transmitter is supported at the output pin of all I/O banks.
Symbol
Parameter
Mode
–I6, –A6, –C7, –I7
Min Max
–A7
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
–C8
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min
5
Max
85
Min
5
Max
85
fHSCLK
Input clock frequency
(high-speed I/O
performance pin)
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
×10
×8
×7
5
5
85
85
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
5
85
5
85
5
85
5
85
5
85
5
85
5
85
5
85
5
85
5
85
5
85
5
170
170
170
170
170
170
170
85
5
170
170
170
170
170
170
170
85
5
170
170
170
170
170
170
170
85
HSIODR
Data rate (high-speed
I/O performance pin)
100
80
70
40
20
10
5
100
80
70
40
20
10
5
100
80
70
40
20
10
5
fHSCLK
Input clock frequency
(low-speed I/O
performance pin)
5
85
5
85
5
85
5
85
5
85
5
85
5
85
5
85
5
85
5
85
5
85
5
85
5
170
170
170
170
5
170
170
170
170
5
170
170
170
170
HSIODR
Data rate (low-speed
I/O performance pin)
100
80
70
100
80
70
100
80
70
Mbps
continued...
Intel® MAX® 10 FPGA Device Datasheet
42
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