Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2017.12.15
Table 24.
Differential HSTL and HSUL I/O Standards Specifications for Intel MAX 10 Devices
I/O Standard
VCCIO (V)
VDIF(DC) (V)
VX(AC) (V)
VCM(DC) (V)
VDIF(AC)
(V)
Min
1.71
1.425
1.14
Typ
1.8
1.5
1.2
Max
1.89
1.575
1.26
Min
Max
—
Min
0.85
0.71
Typ
—
Max
0.95
0.79
Min
0.85
0.71
Typ
—
Max
0.95
0.79
Min
0.4
0.4
0.3
HSTL-18 Class I, II
HSTL-15 Class I, II
HSTL-12 Class I, II
0.2
0.2
—
—
—
0.16
VCCIO
0.48 ×
VCCIO
0.5 ×
VCCIO
0.52 ×
VCCIO
0.48 ×
VCCIO
0.5 ×
VCCIO
0.52 ×
VCCIO
HSUL-12
1.14
1.2
1.3
0.26
—
0.5 ×
0.5 ×
VCCIO
0.5 ×
VCCIO
+ 0.12
0.4 ×
VCCIO
0.5 ×
VCCIO
0.6 ×
VCCIO
0.44
VCCIO
0.12
–
Differential I/O Standards Specifications
Table 25.
Differential I/O Standards Specifications for Intel MAX 10 Devices
(18)
(19)(20)
(19)
I/O Standard
VCCIO (V)
Typ
VID (mV)
VICM (V)
VOD (mV)
VOS (V)
Typ
Min
Max
Min
Max
Min
0.05
0.55
Condition
Max
1.8
Min
Typ
Max
Min
Max
(21)
LVPECL
LVDS
2.375
2.5
2.625
100
—
DMAX ≤ 500 Mbps
—
—
—
—
—
—
500 Mbps ≤ DMAX
700 Mbps
≤
1.8
1.05
0.05
0.55
DMAX > 700 Mbps
DMAX ≤ 500 Mbps
1.55
1.8
2.375
2.5
2.625
100
—
247
—
600
1.125
1.25
1.375
500 Mbps ≤ DMAX
700 Mbps
≤
1.8
continued...
(18)
(19)
(20)
(21)
VIN range: 0 V ≤ VIN ≤ 1.85 V.
RL range: 90 ≤ RL ≤ 110 Ω.
Low VOD setting is only supported for RSDS standard.
LVPECL input standard is only supported at clock input. Output standard is not supported.
Intel® MAX® 10 FPGA Device Datasheet
23
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