Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2017.12.15
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I/O Standard
VCCIO (V)
Typ
VID (mV)
VICM (V)
VOD (mV)
Min Typ
VOS (V)
Typ
Min
Max
Min
100
Max
Min
0.05
0.55
Condition
Max
1.8
Max
Min
Max
HiSpi
2.375
2.5
2.625
—
DMAX ≤ 500 Mbps
—
—
—
—
—
—
500 Mbps ≤ DMAX
700 Mbps
≤
1.8
1.05
DMAX > 700 Mbps
1.55
Related Links
Intel MAX 10 LVDS SERDES I/O Standards Support, Intel MAX 10 High-Speed LVDS I/O User Guide
Provides the list of I/O standards supported in single supply and dual supply devices.
Switching Characteristics
This section provides the performance characteristics of Intel MAX 10 core and periphery blocks.
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VIN range: 0 V ≤ VIN ≤ 1.85 V.
RL range: 90 ≤ RL ≤ 110 Ω.
Low VOD setting is only supported for RSDS standard.
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No fixed VIN , VOD , and VOS specifications for Bus LVDS (BLVDS). They are dependent on the system topology.
Mini-LVDS, RSDS, and Point-to-Point Differential Signaling (PPDS) standards are only supported at the output pins for Intel MAX 10
devices.
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Supported with requirement of an external level shift
Sub-LVDS input buffer is using 2.5 V differential buffer.
Differential output depends on the values of the external termination resistors.
Differential output offset voltage depends on the values of the external termination resistors.
Intel® MAX® 10 FPGA Device Datasheet
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