Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2017.12.15
I/O Standard
VIL(DC) (V)
Min Max
VIH(DC) (V)
VIL(AC) (V)
Min Max
VIH(AC) (V)
VOL (V)
Max
VOH (V)
Min
IOL (mA)
IOH (mA)
Min
Max
Min
Max
HSTL-12 Class I
HSTL-12 Class II
HSUL-12
–0.15
–0.15
—
VREF
0.08
–
VREF
+ 0.08
VCCIO
+ 0.15
–0.24
–0.24
—
VREF
0.15
–
VREF
+ 0.15
VCCIO
+ 0.24
0.25 ×
VCCIO
0.75 ×
VCCIO
8
–8
–14
—
VREF
0.08
–
VREF
+ 0.08
VCCIO
+ 0.15
VREF
0.15
–
VREF
+ 0.15
VCCIO
+ 0.24
0.25 ×
VCCIO
0.75 ×
VCCIO
14
—
VREF
0.13
–
VREF
+ 0.13
—
VREF
0.22
–
VREF
+ 0.22
—
0.1 ×
VCCIO
0.9 ×
VCCIO
Differential SSTL I/O Standards Specifications
Differential SSTL requires a VREF input.
Table 23.
Differential SSTL I/O Standards Specifications for Intel MAX 10 Devices
I/O Standard
VCCIO (V)
Typ
VSwing(DC) (V)
VX(AC) (V)
VSwing(AC) (V)
Min
Max
Min
Max(17)
Min
Typ
Max
Min
Max
SSTL-2 Class I, II
2.375
2.5
2.625
0.36
0.25
0.2
VCCIO
VCCIO/2 –
0.2
—
VCCIO
2+ 0.2
/
0.7
VCCIO
SSTL-18 Class I, II
SSTL-15 Class I, II
SSTL-135
1.7
1.8
1.5
1.9
1.575
1.45
VCCIO
VCCIO/2 –
0.175
—
—
VCCIO
2+ 0.175
/
0.5
VCCIO
1.425
1.283
—
VCCIO/2 –
0.15
VCCIO/2
+ 0.15
2(VIH(AC)
VREF
–
–
2(VIL(AC)
VREF
–
–
)
)
1.35
0.18
—
VREF
–
0.5 × VCCIO
VREF
+ 0.135
2(VIH(AC)
VREF
2(VIL(AC)
VREF
0.135
)
)
Differential HSTL and HSUL I/O Standards Specifications
Differential HSTL requires a VREF input.
(17)
The maximum value for VSWING(DC) is not defined. However, each single-ended signal needs to be within the respective single-ended
limits (VIH(DC) and VIL(DC)).
Intel® MAX® 10 FPGA Device Datasheet
22
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