Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2017.12.15
Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications
Table 21. Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for Intel MAX 10 Devices
(14)
I/O Standard
VCCIO (V)
Typ
2.5
VREF (V)
Typ
VTT (V)
Typ
Min
2.375
1.7
Max
2.625
1.9
Min
1.19
Max
1.31
Min
VREF – 0.04
VREF – 0.04
0.49 × VCCIO
0.49 × VCCIO
0.85
Max
VREF + 0.04
VREF + 0.04
0.51 × VCCIO
0.51 × VCCIO
0.95
SSTL-2 Class I, II
SSTL-18 Class I, II
SSTL-15 Class I, II
SSTL-135 Class I, II
HSTL-18 Class I, II
HSTL-15 Class I, II
HSTL-12 Class I, II
1.25
VREF
1.8
0.833
0.9
0.969
VREF
1.425
1.283
1.71
1.5
1.575
1.45
1.89
1.575
1.26
0.49 × VCCIO
0.49 × VCCIO
0.85
0.5 × VCCIO
0.5 × VCCIO
0.9
0.51 × VCCIO
0.51 × VCCIO
0.95
0.5 × VCCIO
0.5 × VCCIO
0.9
1.35
1.8
1.425
1.14
1.5
0.71
0.75
0.79
0.71
0.75
0.79
(15)
1.2
0.48 × VCCIO
0.5 × VCCIO
0.52 × VCCIO
—
0.5 × VCCIO
—
(15)
(15)
(16)
0.47 × VCCIO
0.5 × VCCIO
0.53 × VCCIO
(16)
(16)
HSUL-12
1.14
1.2
1.3
0.49 × VCCIO
0.5 × VCCIO
0.51 × VCCIO
—
—
—
(14)
(15)
(16)
VTT of transmitting device must track VREF of the receiving device.
Value shown refers to DC input reference voltage, VREF(DC)
Value shown refers to AC input reference voltage, VREF(AC)
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Intel® MAX® 10 FPGA Device Datasheet
20
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