Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2017.12.15
Symbol
Parameter
Condition
Min
Typ
Max
Unit
(29)
fVCO
PLL internal voltage-controlled oscillator (VCO)
operating range
—
600
—
1300
MHz
fINDUTY
Input clock duty cycle
—
40
—
—
—
—
—
—
45
—
—
—
—
—
—
—
—
50
—
60
0.15
±750
472.5
472.5
450
%
UI
(30)
tINJITTER_CCJ
Input clock cycle-to-cycle jitter
FINPFD ≥ 100 MHz
FINPFD < 100 MHz
—
ps
(28)
fOUT_EXT
fOUT
PLL output frequency for external clock output
PLL output frequency to global clock
MHz
MHz
MHz
MHz
%
–6 speed grade
–7 speed grade
–8 speed grade
Duty cycle set to 50%
—
402.5
55
tOUTDUTY
tLOCK
Duty cycle for external clock output
Time required to lock from end of device
configuration
1
ms
tDLOCK
Time required to lock dynamically
After switchover, reconfiguring
any non-post-scale counters or
delays, or when areset is
deasserted
—
—
1
ms
tOUTJITTER_PERIOD_IO
Regular I/O period jitter
FOUT ≥ 100 MHz
FOUT < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
—
—
—
—
—
—
—
—
650
75
ps
mUI
ps
(31)
(31)
tOUTJITTER_CCJ_IO
Regular I/O cycle-to-cycle jitter
650
75
mUI
continued...
(29)
The VCO frequency reported by the Intel Quartus Prime software in the PLL summary section of the compilation report takes into
consideration the VCO post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower
than the fVCO specification.
(30)
(31)
A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source,
which is less than 200 ps.
Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification
applies to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied.
Intel® MAX® 10 FPGA Device Datasheet
27
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