Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2017.12.15
Core Performance Specifications
Clock Tree Specifications
Table 26.
Clock Tree Specifications for Intel MAX 10 Devices
Device
Performance
Unit
–I6
450
450
450
450
450
450
450
–A6, –C7
416
–I7
416
416
416
416
416
416
416
–A7
382
382
382
382
382
382
382
–C8
10M02
10M04
10M08
10M16
10M25
10M40
10M50
402
402
402
402
402
402
402
MHz
MHz
MHz
MHz
MHz
MHz
MHz
416
416
416
416
416
416
PLL Specifications
Table 27.
PLL Specifications for Intel MAX 10 Devices
VCCD_PLL should always be connected to VCCINT through decoupling capacitor and ferrite bead.
Symbol
Parameter
Input clock frequency
Phase frequency detector (PFD) input frequency
Condition
Min
5
Typ
—
Max
472.5
325
Unit
(28)
fIN
—
—
MHz
fINPFD
5
—
MHz
continued...
(28)
This parameter is limited in the Intel Quartus Prime software by the I/O maximum frequency. The maximum I/O frequency is different
for each I/O standard.
Intel® MAX® 10 FPGA Device Datasheet
26
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