AS4C64M8D2
Figure 38. Burst read operation with auto precharge:
(RL=4, AL=1, CL=3, BL=4, tRTP>2 clocks)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK#
CK
Bank A
Activate
Post CAS#
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CMD
>= AL+tRTP+tRP
Autoprecharge
DQS
DQS#
AL= 1
CL= 3
RL= 4
DoutA0 DoutA1 DoutA2 DoutA3
DQ's
tRTP
tRP
First 4-bit prefetch
Precharge begins here
Figure 39. Burst read operation with auto precharge followed by activation to the same
bank (tRC Limit): RL=5(AL=2, CL=3, internal tRCD=3, BL=4, tRTP≦2 clocks)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK#
CK
A10= 1
Bank A
Activate
Post CAS#
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CMD
>=tRAS(min)
Auto Precharge Begins
DQS
DQS#
AL= 2
CL= 3
RL= 5
>=tRP
DoutA0 DoutA1 DoutA2 DoutA3
DQ's
CL=3
>= tRC
Confidential
49
Rev. 1.0
Feb. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
