AS4C64M8D2
Figure 44. Self refresh operation
T0
T1
T2
T3
T4
T5
T6
Tm
Tn
tCK
tCH
tCL
CK#
CK
>=tXSNR
tRP*
>=tXSRD
CKE
VIH(ac)
VIL(ac)
tIS
tAOFD
tIS
VIL(ac)
ODT
CMD
tIS
tIH
tIS
NOP
tIH
Valid
tIS tIH
VIH(ac)
VIL(ac)
VIH(dc)
VIL(dc)
Self
NOP
NOP
Refresh
NOTE 1 Device must be in the "All banks idle" state prior to entering Self Refresh mode.
NOTE 2 ODT must be turned off tAOFD before entering Self Refresh mode, and can be
turned on again when tXSRD timing is satisfied.
NOTE 3 tXSRD is applied for Read or a Read with autoprecharge command.
tXSNR is applied for any command except a Read or a Read with autoprecharge command.
Figure 45. Basic power down entry and exit timing diagram
CK
CK#
tIH
tIS
tIS tIH
tIH
tIS
tIH
CKE
VALID
or NOP
VALID
NOP
NOP
NOP
VALID
Command
tCKE min
tXP, tXARD
tCKE(min)
tXARDS
Exit Power-Down mode
Enter Power-Down mode
Don't Care
Figure 46. CKE intensive environment
CK#
CK
tCKE
tCKE
CKE
tCKE
tCKE
NOTE: DRAM guarantees all AC and DC timing & voltage specifications and proper DLL operation with intensive CKE operation
Confidential
52
Rev. 1.0
Feb. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
