AS4C64M8D2
Figure 47. CKE intensive environment
CK#
CK
CKE
tCKE
tCKE
tCKE
tCKE
tXP
tXP
CMD
REF
REF
tREFI
NOTE: The pattern shown above can repeat over a long period of time. With this pattern, DRAM guarantees all AC and DC timing & voltage
specifications and DLL operation with temperature and voltage drift
Figure 48. Read to power-down entry
T0
T1
T2
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6
Tx+7
Tx+8
Tx+9
CK#
CK
Read operation starts with a read command and
CMD
CKE
RD
CKE should be kept HIGH until the end of burst operation
BL=4
AL+CL
tIS
Q
Q
Q
Q
DQ
DQS
DQS#
T0
T1
T2
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6
Tx+7
Tx+8
Tx+9
CK#
CK
CMD
CKE
RD
CKE should be kept HIGH until the end of burst operation
BL=8
AL+CL
tIS
Q
Q
Q
Q
Q
Q
Q
Q
DQ
DQS
DQS#
Confidential
53
Rev. 1.0
Feb. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
