AS4C64M8D2
Figure 36. Burst write followed by precharge: WL= (RL-1) =4
T0 T1 T2 T3 T4 T5
T6
T7
T9
CK#
CK
Post CAS#
Write A
Precharge A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CMD
Completion of the Burst Write
>=tWR
DQS
DQS#
WL= 4
DNA0 DNA1 DNA2 DNA3
DQ's
Figure 37. Burst read operation with auto precharge:
(RL=4,AL=1, CL=3, BL=8, tRTP≦2 clocks)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK#
CK
Bank A
Activate
Post CAS#
READ A
NOP
NOP
NOP
NOP
NOP
NOP
>= tRP
NOP
CMD
Autoprecharge
AL + BL/2 clks
DQS
DQS#
CL = 3
AL = 1
RL= 4
DOUT
A7
DOUT DOUT DOUT DOUT DOUT DOUT DOUT
A0 A1 A2 A3 A4 A5 A6
DQ's
>=tRTP
tRTP
First 4-bit prefetch
Second 4-bit prefetch
Precharge begins here
Confidential
48
Rev. 1.0
Feb. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
