AS4C64M8D2
Figure 40. Burst read operation with auto precharge followed by an activation to the same
bank (tRP Limit): (RL=5 (AL=2, CL=3, internal tRCD=3, BL=4, tRTP≦2 clocks)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK#
CK
A10= 1
Bank A
Activate
Post CAS#
READ A
NOP
NOP
>=tRAS(min)
NOP
NOP
NOP
NOP
NOP
CMD
Auto Precharge Begins
DQS
DQS#
>= tRP
AL= 2
CL= 3
RL= 5
DoutA0 DoutA1 DoutA2 DoutA3
DQ's
CL=3
>= tRC
Figure 41. Burst write with auto-precharge (tRC Limit): WL=2, WR=2, BL=4, tRP=3
T0
T1
T2
T3
T4
T5
T6
T7
Tm
CK#
CK
A10 = 1
Bank A
Active
Post CAS#
WRA Bank A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CMD
Completion of the Burst Write
Auto Precharge Begins
DQS
DQS#
WL= RL-1=2
>=WR
>=tRP
DNA0 DNA1 DNA2 DNA3
DQ's
>=tRC
Confidential
50
Rev. 1.0
Feb. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
