AS4C64M8D2
Figure 34. Burst read operation followed by precharge:
(RL=4, AL=0, CL=4, BL=8, tRTP>2 clocks)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK#
CK
Bank A
Activate
Post CAS#
READ A
Precharge A
NOP
NOP
NOP
NOP
NOP
NOP
CMD
AL + 2 + max( tRTP, 2 tCK)*
DQS
DQS#
CL = 4
RL= 4
AL = 0
>=tRP
DQ's
DOUT
A7
DOUT DOUT DOUT DOUT DOUT DOUT DOUT
A0
A1
A2
A3
A4
A5
A6
>=tRAS
>=tRTP
First 4-bit prefetch
Second 4-bit prefetch
*: rounded to next integer.
Figure 35. Burst write operation followed by precharge: WL= (RL-1) =3
T0 T1 T2 T3 T4 T5 T6
T7
T8
CK#
CK
Post CAS#
Write A
Precharge A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CMD
Completion of the Burst Write
>=tWR
DQS
DQS#
WL= 3
DNA0 DNA1 DNA2 DNA3
DQ's
Confidential
47
Rev. 1.0
Feb. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
