[AK4679]
7-2. RAM Writing Timing during RUN
These operations are to rewrite Coefficient RAM (CRAM) and Offset REG (OFREG) during RUN. Data writing is
executed in 2step; write preparation and write execution. The writing data can be confirmed by reading write preparation
data.
1. Write Preparation
After inputting the assigned command code (8-bit) to select the number of data from 1 to 16, input the starting
address of write (16-bit all 0) and the number of data assigned by command code in this order.
2. Write Preparation Data Confirmation
After write preparation, prepared data for writing can be confirmed. Address and Data are read in this order by write
preparation data confirmation command “24h”. The data will be “0x000001” when reading more than write
preparation data. Execute write preparation again when the address and data are garbled by external noise.
3. Write Execution
Upon completion of this operation, execute RAM write during RUN by inputting the corresponding command code
and address (16-bit all “0”) in this order.
Note 90. Execute Write preparation before a write execution. When writing to RAM without write preparation
sequence, a malfunction occurs. Access operation by microcontroller is prohibited until RDY changes to
“H”.
Write modification of RAM contents is executed whenever the RAM address for modification is assigned. For
example, when 5 Data are written, from RAM address “10”, it is executed as shown below.
RAM execution address
Write execution position
7
8
9
10 11 13 16 11 12 13 14 15
↓
↓
↓
↓
↓
○
○
↑
○
○
○
Note: Address “13” is not executed until rewriting address “12”.
DSPRSTN bit= “1”
CSN
(Ex.) When # of DATA is 4
CRAM Command Code0x83
OFREG Command Code 0x93
SCLK
don’tcare
don’tcare
(L/H)
Command Address DATA0
Code
DATA1
DATAn-1 DATAn
SI
(L/H)
CRAM 0x80(# of DATA: 1)~0x8F(# of DATA: 16)
OFREG 0x90(# of DATA: 1)~0x9F(# DATA: 16)
Figure 140. CRAM/OFREG Write Preparation
MS1402-E-06
2013/02
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AKM [ ASAHI KASEI MICROSYSTEMS ]
