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AK4675 参数 Datasheet PDF下载

AK4675图片预览
型号: AK4675
PDF下载: 下载PDF文件 查看货源
内容描述: 立体声编解码器与MIC / RCV / HP / SPK- AMP [Stereo CODEC with MIC/RCV/HP/SPK-AMP]
分类和应用: 解码器编解码器
文件页数/大小: 178 页 / 2136 K
品牌: AKM [ ASAHI KASEI MICROSYSTEMS ]
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[AK4675]  
EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)  
When PMPLL bit is “0”, the AK4675 becomes EXT mode. Master clock is input from the MCKI pin, the internal PLL  
circuit is not operated. This mode is compatible with I/F of the normal audio CODEC. The clocks required to operate are  
MCKI (256fs, 384fs, 512fs, 768fs or 1024fs), LRCK (fs) and BICK (32fs). The master clock (MCKI) should be  
synchronized with LRCK. The phase between these clocks does not matter. The input frequency of MCKI is selected by  
FS1-0 bits (Table 11).  
In case that the CODEC is used without Audio I/F (like phone call), the CODEC can be operated by MCKI only. In this  
case, BICK and LRCK can be stopped.  
MCKI Input  
Frequency  
Sampling Frequency  
Range  
Mode  
FS3 bit  
FS2 bit  
FS1 bit  
FS0 bit  
x
0
1
4
5
6
7
0
0
1
1
1
1
0
0
0
0
1
1
0
1
0
1
0
1
256fs  
1024fs  
384fs  
768fs  
512fs  
256fs  
N/A  
8kHz 48kHz  
8kHz 13kHz  
8kHz 48kHz  
8kHz 26kHz  
8kHz 26kHz  
8kHz 48kHz  
N/A  
x
x
x
x
x
(default)  
Others  
Others  
(N/A: Not available, x: Don’t care)  
Table 11. MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)  
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.  
The out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output  
through LOUT/ROUT pins at fs=8kHz is shown in Table 12.  
S/N  
MCKI  
(fs=8kHz, 20kHzLPF + A-weighted)  
256fs  
512fs  
1024fs  
83dB  
93dB  
93dB  
Table 12. Relationship between MCKI and S/N of LOUT1/ROUT1 pins  
The external clocks (MCKI, BICK and LRCK) should always be present whenever the ADC or DAC is in operation  
(PMADL bit = “1”, PMADR bit = “1”, PMDAL bit = “1” or PMDAR bit = “1”). If these clocks are not provided, the  
AK4675 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic  
internally. If the external clocks are not present, the ADC and DAC should be in the power-down mode  
(PMADL=PMADR=PMDAL=PMDAR bits = “0”).  
AK4675  
MCKO  
DSP or μP  
256fs, 384fs, 512fs,  
768fs or 1024fs  
MCKI  
BICK  
LRCK  
MCLK  
BCLK  
LRCK  
32fs  
1fs  
SDTI  
SDTO  
SDTI  
SDTO  
Figure 42. EXT Slave Mode  
MS0963-E-00  
2008/05  
- 57 -  
 
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