[AK4675]
■ System Reset
The PDNA pin must keep “L” until all power supply pins are supplied, and must be set to “H”. After exiting reset (PDNA
pin: “L” Æ “H”), all blocks of HP/SPK-Amp blocks (Input Volume, VCOMA, Oscillator, Mixer, Headphone-Amp,
Speaker-Amp and charge pump circuit) switch to the power-down state. The contents of the control register are
maintained until this reset by the PDNA pin.
Upon power-up, CODEC & SRC blocks of the AK4675 must be reset by bringing the PDN pin = “L”. This ensures that
all internal registers of CODEC & SRC blocks reset to their initial values.
The ADC enters initialization cycle when the PMADL or PMADR bit is changed from “0” to “1” if PMDAL and
PMDAR bits are “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During initialization cycle, the ADC
digital data outputs of both channels are forced to a 2’s complement, “0”. The ADC output reflects the analog input signal
after the initialization cycle is complete. When PMDAL or PMDAR is “1”, the ADC does not require an initialization
cycle.
MS0963-E-00
2008/05
- 59 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
