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AK4675 参数 Datasheet PDF下载

AK4675图片预览
型号: AK4675
PDF下载: 下载PDF文件 查看货源
内容描述: 立体声编解码器与MIC / RCV / HP / SPK- AMP [Stereo CODEC with MIC/RCV/HP/SPK-AMP]
分类和应用: 解码器编解码器
文件页数/大小: 178 页 / 2136 K
品牌: AKM [ ASAHI KASEI MICROSYSTEMS ]
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[AK4675]  
When PLL reference clock input is LRCK or BICK pin, the sampling frequency is selected by FS3-2 bits (Table 6).  
Mode  
0
1
2
FS3 bit  
FS2 bit  
FS1 bit  
Don’t care  
Don’t care  
Don’t care  
FS0 bit  
Don’t care  
Don’t care  
Don’t care  
Sampling Frequency Range  
0
0
1
0
1
8kHz fs 12kHz  
12kHz < fs 24kHz  
24kHz < fs 48kHz  
N/A  
Don’t care  
(default)  
Others  
Others  
Table 6. Setting of Sampling Frequency at PMPLL bit = “1” (Reference Clock = LRCK or BICK pin)  
PLL Unlock State  
1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)  
In this mode, the LRCK and BICK pins go to “L” and irregular frequency clock is output from the MCKO pins at MCKO  
bit is “1” before the PLL goes to lock state after PMPLL bit = “0” Æ “1”. If MCKO bit is “0”, the MCKO pin goes to “L”.  
(Table 7)  
After the PLL is locked, a first period of LRCK and BICK may be invalid clock, but these clocks return to normal state  
after a period of 1/fs.  
When sampling frequency is changed, the BICK and LRCK pins do not output irregular frequency clocks but go to “L” by  
setting PMPLL bit to “0”.  
MCKO pin  
MCKO bit = “0” MCKO bit = “1”  
PLL State  
BICK pin  
LRCK pin  
After that PMPLL bit “0” Æ “1”  
PLL Unlock (except above case)  
PLL Lock  
“L” Output  
“L” Output  
“L” Output  
Invalid  
Invalid  
See Table 9  
“L” Output  
Invalid  
See Table 10  
“L” Output  
Invalid  
1fs Output  
Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)  
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)  
In this mode, an invalid clock is output from the MCKO pin before the PLL goes to lock state after PMPLL bit = “0” Æ  
“1”. After that, the clock selected by Table 9 is output from the MCKO pin when PLL is locked. ADC and DAC output  
invalid data when the PLL is unlocked. For DAC, the output signal should be muted by writing “0” to DACL, DACR,  
DACH and DACS bits.  
MCKO pin  
PLL State  
MCKO bit = “0” MCKO bit = “1”  
After that PMPLL bit “0” Æ “1”  
PLL Unlock  
PLL Lock  
“L” Output  
“L” Output  
“L” Output  
Invalid  
Invalid  
Output  
Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “0”, M/S bit = “0”)  
MS0963-E-00  
2008/05  
- 53 -  
 
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