[AK4675]
■ PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz or 27MHz)
is input to the MCKI pin, the MCKO, BICK and LRCK clocks are generated by an internal PLL circuit. The MCKO
output frequency is selected by PS1-0 bits (Table 9) and the output is enabled by MCKO bit. The BICK output frequency
is selected between 32fs or 64fs, by BCKO bit (Table 10).
11.2896MHz, 12MHz, 12.288MHz, 13MHz,
13.5MHz, 19.2MHz, 24MHz, 26MHz,
27MHz
AK4675
DSP or μP
MCKI
256fs/128fs/64fs/32fs
MCLK
BCLK
LRCK
MCKO
BICK
32fs, 64fs
1fs
LRCK
SDTI
SDTO
SDTI
SDTO
Figure 38. PLL Master Mode
Mode
PS1 bit
PS0 bit
MCKO pin
0
1
2
3
0
0
1
1
0
1
0
1
256fs
128fs
64fs
(default)
32fs
Table 9. MCKO Frequency (PLL mode, MCKO bit = “1”)
BCKO bit
BICK Output Frequency
0
1
32fs
64fs
(default)
Table 10. BICK Output Frequency at Master Mode
MS0963-E-00
2008/05
- 54 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
