[AK4675]
■ PLL Mode (PMPLL bit = “1”)
When PMPLL bit is “1”, an integrated analog phase locked loop (PLL) generates a clock that is selected by the PLL3-0
and FS3-0 bits. The PLL lock time is shown in Table 4, when the AK4675 is supplied stable clock after PLL is
powered-up (PMPLL bit = “0” → “1”) or sampling frequency is changed. When AIN3 bit = “1”, the PLL is not available.
1) Setting of PLL Mode
R and C of
VCOC pin
PLL Lock
Time
(max)
PLL3
bit
PLL2
bit
PLL1
bit
PLL0
bit
PLL Reference
Clock Input Pin
Input
Frequency
Mode
C[F]
R[Ω]
0
2
0
0
0
0
0
1
0
0
LRCK pin
BICK pin
1fs
6.8k
10k
10k
10k
10k
10k
10k
10k
10k
10k
10k
10k
10k
10k
220n
4.7n
10n
4.7n
10n
4.7n
4.7n
10n
10n
4.7n
10n
10n
220n
220n
160ms
2ms
4ms
2ms
4ms
40ms
40ms
40ms
40ms
40ms
40ms
40ms
60ms
60ms
32fs
3
0
0
1
1
BICK pin
64fs
4
5
6
7
8
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
1
1
0
0
0
1
1
0
1
0
1
0
0
1
0
1
MCKI pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
N/A
11.2896MHz
12.288MHz
12MHz
(default)
24MHz
19.2MHz
13.5MHz
27MHz
13MHz
26MHz
12
13
14
15
Others
Others
Table 4. Setting of PLL Mode (*fs: Sampling Frequency)
2) Setting of sampling frequency in PLL Mode
When PLL reference clock input is MCKI pin, the sampling frequency is selected by FS3-0 bits as defined in Table 5.
Mode
0
1
2
3
FS3 bit
FS2 bit
FS1 bit
FS0 bit
Sampling Frequency
8kHz
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
0
0
1
0
0
1
1
0
1
1
1
1
0
1
0
1
1
1
0
1
1
12kHz
16kHz
24kHz
11.025kHz
22.05kHz
32kHz
48kHz
44.1kHz
N/A
5
7
10
11
15
Others
(default)
Others
Table 5. Setting of Sampling Frequency at PMPLL bit = “1” (Reference Clock = MCKI pin)
MS0963-E-00
2008/05
- 52 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
