[AK4492]
■ System Clock
[1] PCM Mode
The external clocks, which are required to operate the AK4492, are MCLK, BICK and LRCK. MCLK, BICK
and LRCK should be synchronized but the phase is not critical. The MCLK is used to operate the digital
interpolation filter, the delta•sigma modulator and SCF.
There are Manual Setting Mode, Auto Setting Mode and Fs Auto Detection mode for MCLK frequency
setting(Table 5). In manual setting mode (ACKS pin=“L” or ACKS bit=“0”), MCLK frequency is set
automatically but the sampling speed (LRCK frequency) is set by DFS[2:0] bits (Table 6). Sampling
frequency is fixed to normal speed mode in pin control mode (PSN pin = “H”), and it is set by DFS[2:0] bits
in register control mode (PSN pin = “L”). In register control mode, the AK4492 is in manual setting mode
when power-down is released (PDN pin = “L” → “H”).
In auto setting mode (ACKS pin = “H” or ACKS bit=“1”), sampling speed and MCLK frequency are
detected automatically (Table 7, Table 11) and then the initial master clock is set to the appropriate
frequency (Table 8, Table 9, Table 15, Table 16).
In FS auto detect mode (AFSD bit= “1”), sampling speed is automatically detected (Table 7, Table 11)
and the initial master clock is set to the appropriate frequency. In this mode, ACKS bit and DFS[2:0] bits
settings are invalid. Fs auto detect mode is not supported by pin control mode.
The AK4492 is automatically placed in power-down state when MCLK is stopped for more than 1us
during a normal operation (PDN pin =“H”), and the analog output becomes Hi-z state. When MCLK is
input again, the AK4492 exits power-down state and starts operation. The AK4492 is in power-down
mode until MCLK BICK and LRCK are supplied and the analog output is floating state.
Table 5. System Clock Setting Mode @Register Control Mode
AFSD bit ACKS bit
Mode
0
1
x
Manual setting Mode
Auto setting Mode
FS Auto Detect Mode
(default)
0
1
(x: Do not care)
016011073-E-00
2016/12
- 40 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
