[AK4359A]
■ Reset Function (MCLK, BICK and LRCK stop)
When the MCLK, LRCK or BICK stops, the digital circuit of the AK4359A is placed in power-down mode. When the
MCLK, LRCK and BICK are restarted, power-down mode is released and the AK4359A returns to normal operation
mode.
AVDD pin
DVDD pin
(1)
RSTB pin
Internal
State
Power-down
Power-down
Normal Operation
Digital Circuit Power-down
Normal Operation
D/A In
(Digital)
(3)
GD (2)
GD (2)
(4)
(5)
(4)
Hi-Z
(5)
D/A Out
(Analog)
(4)
(6)
Clock In
MCLK, BICK, LRCK
MCLK, BICK, LRCK Stop
External
MUTE
(6)
(6)
Notes:
(1) After AVDD and DVDD are powered-up, the PDN pin should be “L” for 150ns.
(2) The analog output corresponding to digital input has group delay (GD).
(3) The digital data can be stopped. Click noise after MCLK, BICK and LRCK are input again can be reduced by
inputting “0” data during this period.
(4) Click noise occurs within 20usec or 20usec +3 ~ 4LRCK from the riding edge (“↑”) of the RSTN pin or MCLK
inputs. Click noise also occurs within 20usec when MCLK, LRCK or BICK is stopped.
(5) Mute the analog output externally if click noise (4) influences system applications. The timing example is shown
in this figure.
Figure 14. Clock Stop Sequence
MS1010-E-01
2008/10
- 22 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
