[AK4359A]
■ De-emphasis Filter
A digital de-emphasis filter is available for 32kHz, 44.1kHz or 48kHz sampling rates (tc = 50/15μs). For double speed
and quad speed modes, the digital de-emphasis filter is always off. In serial control mode, the DEM1-0 bits are enabled
for each DAC by the DEMA-D bits setting. In parallel control mode, DEM1-0 pins are valid.
DEM1
DEM0
Mode
0
0
1
1
0
1
0
1
44.1kHz
OFF
(default)
48kHz
32kHz
Table 9. De-emphasis Filter Control (Normal Speed Mode)
■ Output Volume Control
The AK4359A includes channel independent digital output volume control (ATT) with 256 levels at linear step including
MUTE. The volume control is in front of the DAC, and it can attenuate the input data from 0dB to –48dB and mute. When
changing levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions. The
transition time of 1 level and all 256 levels is shown in Table 10. The attenuation level is calculated by ATT = 20 log10
(ATT_DATA / 255) [dB] and MUTE at ATT_DATA = “0”.
Sampling Speed
Transition Time
255 to 0
1 Level
4LRCK
8LRCK
16LRCK
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
1020LRCK
2040LRCK
4080LRCK
Table 10. ATT Transition time
■ Zero Detection
When the input data at all channels are continuously zeros for 8192 LRCK cycle, the zero detection is executed (Table
11). The DZF pin is immediately set to “L” if input data of each channel is not zero after going DZF “H”. If RSTN bit is
“0”, the DZF pin is set to “H”. The DZF pin goes “L” after 4~5LRCK after RSTN bit returns to “1”. Zero detect function
can be disabled by setting the DZFE bit. In this case, all DZF pins are always “L”. When one of PW1-4 bit is set to “0”, the
input data of DAC, that the PW bit is set to “0”, should be zero in order to enable zero detection of the other channels.
When all PW1-4 bits are set to “0”, the DZF pin fixes “L”. DZFB bit can invert the polarity of the DZF pin. In parallel
control mode, the zero detect function is disabled and the DZF pin is fixed to “L”.
DZF Pin
DZF1
DZF2
Operations
ANDed output of zero detection flag of each channel set to “1” in 0CH register
ANDed output of zero detection flag of each channel set to “1” in 0DH register
Table 11. DZF pins Operation
MS1010-E-01
2008/10
- 18 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
