[AK4359A]
■ Soft Mute Operation
The Soft mute operation is performed in the digital domain. When the SMUTE bit is set to “1”, the output signal is
attenuated by -∞ during ATT_DATA×ATT transition time (Table 10) from the current ATT level. When the SMUTE bit
is returned to “0”, the mute is cancelled and the output attenuation gradually changes to the ATT level during
ATT_DATA×ATT transition time. If the soft mute is cancelled before attenuating to -∞ after starting the operation, the
attenuation is discontinued and returned to ATT level by the same cycle. The soft mute is effective for changing the signal
source without stopping the signal transmission.
SMUTE
(1)
(1)
ATT Level
Attenuation
(3)
-∞
GD
GD
(2)
AOUT
(4)
8192/fs
DZF pin
Notes:
(1) ATT_DATA×ATT transition time (Table 10). For this example, in Normal Speed Mode, the time is 1020LRCK
cycles (1020/fs) at ATT_DATA=255.
(2) The analog output corresponding to the digital input has a group delay, GD.
(3) If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and
returned to ATT level by the same cycle.
(4) When the input data for each channel is continuously zero for 8192 LRCK cycles, the DZF pin for each channel
changes to “H”. The DZF pin immediately goes “L” if input data are not zero after going DZF “H”. In parallel control
mode, the DZF pin is fixed to “L” regardless of the state of the SMUTE pin.
Figure 11. Soft Mute and Zero Detection (DZFB bit = “0”)
MS1010-E-01
2008/10
- 19 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
