[AK4359A]
(2) I2C-bus Control Mode (I2C pin = “H”)
The AK4359A supports the fast-mode I2C-bus system (max: 400kHz).
Figure 16 shows the data transfer sequence at the I2C-bus mode. All commands are preceded by a START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 20). After the
START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit which is a data direction
bit (R/W) (Figure 17). The most significant six bits of the slave address are fixed as “001001”. The next one bit are CAD0
(device address bit). The bit identify the specific device on the bus. The hard-wired input pin (CAD0 pin) set them. If the
slave address match that of the AK4359A and R/W bit is “0”, the AK4359A generates the acknowledge and the write
operation is executed. If R/W bit is “1”, the AK4359A generates the not acknowledge since the AK4359A can be only a
slave-receiver. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during
the acknowledge clock pulse (Figure 21).
The second byte consists of the address for control registers of the AK4359A. The format is MSB first, and those most
significant 3-bits are fixed to zeros (Figure 18). Those data after the second byte contain control data. The format is MSB
first, 8bits (Figure 19). The AK4359A generates an acknowledge after each byte is received. A data transfer is always
terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is
HIGH defines a STOP condition (Figure 20).
The AK4359A is capable of more than one byte write operation by one sequence. After receipt of the third byte, the
AK4359A generates an acknowledge, and awaits the next data. The master can transmit more than one byte instead of
terminating the write cycle after the first data byte is transferred. After the receipt of each data, the internal 5bits address
counter is incremented by one, and the next data is taken into next address automatically. If the addresses exceed 1FH
prior to generating the stop condition, the address counter will “roll over” to 00H and the previous data will be
overwritten.
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW (Figure 22) except for the START and the STOP
condition.
S
S
T
O
P
T
A
R
T
R/W
Slave
Address
Sub
Address(n)
S
Data(n)
Data(n+1)
Data(n+x)
P
SDA
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 16. Data transfer sequence at the I2C-bus mode
0
0
0
1
0
0
1
CAD0
R/W
(This CAD0 should match with CAD0 pin)
Figure 17. The first byte
0
0
A4
A3
A2
A1
D1
A0
D0
Figure 18. The second byte
D7
D6
D5
D4
D3
D2
Figure 19. Byte structure after the second byte
MS1010-E-01
2008/10
- 24 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
