ASAHI KASEI
[AK4115]
2-2. WRITE Operations
Set R/W bit = “0” for the WRITE operation of AK4115.
After receipt the start condition and the first byte, the AK4115 generates an acknowledge, and awaits the second byte
(register address). The second byte consists of the address for control registers of AK4115. The format is MSB first,
8-bits.
A7
A6
A5
A4
A3
A2
A1
A0
Figure 45. The Second Byte
After receipt of the second byte, the AK4115 generates an acknowledge, and awaits the third byte. Those data after the
second byte contain control data. The format is MSB first, 8-bits.
D7
D6
D5
D4
D3
D2
D1
D0
Figure 46. Byte structure after the second byte
The AK4115 is capable of more than one byte write operation by one sequence.
After receipt of the third byte, the AK4115 generates an acknowledge, and awaits the next data again. The master can
transmit more than one word instead of terminating the write cycle after the first data word is transferred. After the
receipt of each data, the internal 5-bit address counter is incremented by one, and the next data is taken into next address
automatically. If the address exceed 49H prior to generating the stop condition, the address counter will “roll over” to
00H and the previous data will be overwritten.
S
S
T
O
P
T
A
R
T
Slave
Address
Register
Address(n)
Data(n)
Data(n+1)
Data(n+x)
S
P
SDA
A
C
K
A
C
K
A
C
K
A
C
K
Figure 47. WRITE Operation
MS0573-E-00
2006/12
- 46 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
