Table 3. Pin Definitions for HDMP-0452.
Pin Name
Pin Pin Type Pin Description
HS_OUT Serial Data Outputs: High-speed outputs to a hard disk drive or to a cable input.
TO_NODE[0]+ 24
TO_NODE[0]– 25
TO_NODE[1]+ 07
TO_NODE[1]– 06
TO_NODE[2]+ 44
TO_NODE[2]– 43
TO_NODE[3]+ 38
TO_NODE[3]– 37
TO_NODE[4]+ 31
TO_NODE[4]– 30
FM_NODE[0]+ 10
FM_NODE[0]– 09
FM_NODE[1]+ 04
FM_NODE[1]– 03
FM_NODE[2]+ 41
FM_NODE[2]– 40
FM_NODE[3]+ 35
FM_NODE[3]– 34
FM_NODE[4]+ 28
FM_NODE[4]– 27
HS_IN
Serial Data Inputs: High-speed inputs from a hard disk drive or from a cable output.
BYPASS[0]– 14
BYPASS[1]– 15
BYPASS[2]– 16
BYPASS[3]– 17
BYPASS[4]– 18
I-LVTTL
Bypass Inputs: For “disk bypassed” mode, connect BYPASS[n]– to GND through
a 1 kΩ resistor. For “disk in loop” mode, float HIGH.
REFCLK
13
I-LVTTL Reference Clock: A user-supplied clock reference used for frequency acquisition in
the Clock and Data Recovery (CDR) circuit.
CPLL1
CPLL0
21
22
C
Loop Filter Capacitor: A loop filter capacitor for the internal Clock and Data Recovery
(CDR) circuit must be connected across the CPLL1 and CPLL0 pins. Recommended
value is 0.1 µF.
SD
19
O-LVTTL Signal Detect: Indicates acceptable signal amplitude on the FM_NODE[0]± inputs.
If (FM_NODE[0]+ – FM_NODE[0]–) >= 400 mV peak-to-peak, SD = 1
If 400 mV > (FM_NODE[0]+ – FM_NODE[0]–) > 100 mV, SD = unpredictable
If 100 mV >= (FM_NODE[0]+ – FM_NODE[0]–), SD = 0
GND
01
08
11
12
23
33
39
S
Ground: Normally 0 volts. See Figure 11 for Recommended Power Supply Filtering.
VCCA
32
S
Analog Power Supply: Normally 3.3 volts. Used to provide a clean supply line for the
Clock and Data Recovery (CDR) circuit. See Figure 11 for Recommended Power
Supply Filtering.
VCCHS[0]
VCCHS[1]
VCCHS[2]
VCCHS[3]
VCCHS[4]
26
05
42
36
29
S
S
S
S
S
High Speed Supply: Normally 3.3 volts. Used only for high-speed outputs
(TO_NODE[n]). See Figure 11 for Recommended Power Supply Filtering.
VCC
02
20
S
Logic Power Supply: Normally 3.3 volts. Used for internal logic.
See Figure 11 for Recommended Power Supply Filtering.
5
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