SD
SD
EQU
TTL
EQU
TTL
EQU
TTL
EQU
TTL
EQU
TTL
BLL
BLL
BLL
BLL
BLL
1
1
1
1
1
0
0
0
0
0
CDR
CPLL
TTL
REFCLK
Figure 1. Block diagram of HDMP-0452.
Table 1. Truth Table for CDR at Entry Configuration.
TO_LOOP
TO_NODE[4]
FM_LOOP
TO_NODE[3]
TO_NODE[2]
FM_LOOP
TO_NODE[1]
BYPASS[4]–
BYPASS[3]– BYPASS[2]– BYPASS[1]–
FM_LOOP
FM_LOOP
FM_LOOP
FM_LOOP
FM_LOOP
FM_LOOP
FM_LOOP
FM_LOOP
FM_LOOP
FM_LOOP
FM_LOOP
FM_LOOP
FM_LOOP
FM_LOOP
FM_LOOP
FM_LOOP
FM_LOOP
FM_LOOP
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
FM_NODE[1]
FM_NODE[2]
FM_NODE[2]
FM_NODE[3]
FM_NODE[3]
FM_NODE[3]
FM_NODE[3]
FM_NODE[4]
FM_NODE[4]
FM_NODE[4]
FM_NODE[4]
FM_NODE[4]
FM_NODE[4]
FM_NODE[4]
FM_NODE[4]
FM_NODE[1]
FM_NODE[2]
FM_NODE[2]
FM_NODE[3]
FM_NODE[3]
FM_NODE[3]
FM_NODE[3]
FM_LOOP
FM_NODE[1] FM_NODE[1]
FM_NODE[2] FM_LOOP
FM_NODE[2] FM_NODE[1]
FM_LOOP
FM_LOOP
FM_NODE[1] FM_NODE[1]
FM_NODE[2] FM_LOOP
FM_NODE[2] FM_NODE[1]
FM_LOOP
FM_LOOP
FM_NODE[1]
FM_NODE[2]
FM_NODE[2]
FM_NODE[3]
FM_NODE[3]
FM_NODE[3]
FM_NODE[3]
FM_NODE[1] FM_NODE[1]
FM_NODE[2] FM_LOOP
FM_NODE[2] FM_NODE[1]
FM_LOOP
FM_LOOP
FM_NODE[1] FM_NODE[1]
FM_NODE[2] FM_LOOP
FM_NODE[2] FM_NODE[1]
Note: FM_LOOP = FM_NODE[0], TO_LOOP = TO_NODE[0], BYPASS[0]– = 1.
Table 2. Pin Connection Diagram to Achieve Desired CDR Location (see Figures 3, 4).
Hard Disks
A B C D
1 2 3 4
xA B C D
0
A B C D
0 1 2 3
AxB C D
4
A B C D
4 0 1 2
A BxC D
3
A B C D
3 4 0 1
A B CxD
2
A B C D
2 3 4 0
A B C Dx
1
Connection to PBC Cells
CDR Position (x)
Cell Connected to Cable
Note: x denotes CDR position with respect to hard disks.
3
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