Agilent HDMP-0452
Quad Port Bypass Circuit
with CDR for Fibre Channel
Arbitrated Loops
Data Sheet
Description
The HDMP-0452 is a Quad Port
Bypass Circuit (PBC) with a Clock
and Data Recovery (CDR) circuit
included. This device minimizes
part count, cost and jitter accumula-
tion while repeating incoming sig-
nals. Port Bypass Circuits are used
in hard disk arrays constructed in
Fibre Channel Arbitrated Loop
(FC-AL) configurations. By using
Port Bypass Circuits, hard disks
may be pulled out or swapped while
other disks in the array are available
to the system.
A Port Bypass Circuit (PBC) con-
sists of multiple 2:1 multiplexers
daisy chained along with a CDR.
Each port has two modes of opera-
tion: “disk in loop” and “disk by-
passed”. When the “disk in loop”
mode is selected, the loop goes into
and out of the disk drive at that
port. For example, data goes from
the HDMP-0452’s TO_NODE[n]±
differential output pins to the Disk
Drive Transceiver IC’s (e.g., an
HDMP-1536A) Rx± differential
input pins. Data from the Disk Drive
Transceiver IC’s Tx± differential
outputs goes to the HDMP-0452’s
FM_NODE[n]± differential input
pins. Figures 3 and 4 show con-
nection diagrams for disk drive
array applications. When the “disk
bypassed” mode is selected, the
disk drive is either absent or non-
functional and the loop bypasses
the hard disk.
The “disk bypassed” mode is
enabled by pulling the
BYPASS[n]– pin low. Leave
BYPASS[n]– floating to enable
the “disk in loop” mode. HDMP-
0452s may be cascaded with other
members of the HDMP-04XX/
HDMP-05XX family through the
FM_LOOP and TO_LOOP pins to
accommodate any number of hard
disks. See Table 2 to identify
which of the 5 cells (0:4) will
provide FM_LOOP and TO_LOOP
pins (cable connections). The
unused cells in this PBC may be
bypassed by using pulldown
resistors on the BYPASS[n]– pins
for these cells.
Features
• Supports 1.0625 GBd fibre
channel operation
• Supports 1.25 GBd Gigabit
Ethernet (GE) operation
• Quad PBC/CDR in one package
• CDR location determined by
choice of cable input/output
• Valid amplitude detection on
FM_NODE[0] input
• Equalizers on all inputs
• High speed LVPECL I/O
• Buffered Line Logic (BLL) outputs
(no external bias resistors
required)
• 0.66 W typical power at
V
CC
= 3.3 V
• 44 pin, 10 mm, low cost plastic
QFP package
Applications
• RAID, JBOD, BTS cabinets
• 1 => 1-4 serial buffer with or
w/o CDR
HDMP-0452
CAUTION: As with all semiconductor ICs, it is advised that normal static precautions be taken in the handling and assem-
bly of this component to prevent damage and/or degradation which may be induced by Electrostatic Discharge (ESD).
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
