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HDMP-0452 参数 Datasheet PDF下载

HDMP-0452图片预览
型号: HDMP-0452
PDF下载: 下载PDF文件 查看货源
内容描述: 四端口旁路电路与CDR的光纤通道仲裁环 [Quad Port Bypass Circuit with CDR for Fibre Channel Arbitrated Loops]
分类和应用: 光纤
文件页数/大小: 12 页 / 275 K
品牌: AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
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Figure 5. Eye diagram of FM_NODE[1]± high-speed differential output.  
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Note: Measurement taken with a 2 -1 PRBS input to FM_NODE[0]±.  
RANDOM JITTER  
HP70841B  
PATTERN  
GENERATOR  
HDMP-0452  
± FM_NODE[0]  
BYPASS[0]–  
2
± DATA  
N/C  
BIAS TEE  
BYPASS[1:4]–  
K28.7  
CLOCK  
REFCLK  
± TO_NODE[0]  
1 k  
1.4 V  
1062.5 MHz  
2
106.25 MHz  
1/10  
HP70311A  
CLOCK SOURCE  
CH 1/2  
106.25 MHz  
TRIGGER  
HP83480A  
DIGITAL  
COMMUNICATION  
ANALYZER  
Figure 6. Setup for measurement of random jitter.  
DETERMINISTIC JITTER  
HP70841B  
PATTERN  
GENERATOR  
HDMP-0452  
2
± FM_NODE[0]  
± DATA  
BYPASS[0]–  
N/C  
BIAS TEE  
BYPASS[1:4]–  
+K28.5 –K28.5  
CLOCK  
REFCLK  
± TO_NODE[0]  
1 kΩ  
1062.5 MHz  
1.4 V  
2
106.25 MHz  
1/10  
HP70311A  
CLOCK SOURCE  
CH 1/2  
TRIGGER  
1/2  
106.25 MHz  
53.125 MHz  
HP83480A  
DIGITAL  
COMMUNICATION  
ANALYZER  
Figure 7. Setup for measurement of deterministic jitter.  
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