An HDMP-0452 may also be used
as five 1:1 buffers, one with a
CDR and four without. For ex-
ample, an HDMP-0452 may be
placed in front of a CMOS ASIC
to clean the jitter of the outgoing
signal (CDR path) and to better
read the incoming signal (non-
CDR path). In addition, the
HDMP-0452 may be configured
as two 2:1 multiplexers or as two
1:2 buffers.
The HDMP-0452 design allows
for CDR placement at any loca-
tion with respect to the hard disk
slots. For example, if the BY-
PASS[0]– pin is floating and hard
disk slots A to D are connected to
PBC cells 1 to 4 respectively (see
Figure 3), the CDR function will
be performed before entering the
hard disk at slot A. To obtain a
CDR function after slot D (see
Figure 4), BYPASS[1]– must be
floating and hard disk slots A to
D must be connected to PBC cells
2,3,4, and 0 respectively. Table 2
shows all possible connections.
For configurations where the
CDR is before slot A, a Signal
Detect (SD) pin shows the status
of the signal at the incoming
cable.
HDMP-0452 Block Diagram
CDR
training controls. It does this by
continually frequency locking
onto the 106.25 MHz reference
clock (REFCLK) and then phase
locking onto the input data
stream. Once bit locked, the CDR
generates a high-speed sampling
clock. This clock is used to
sample or repeat the incoming
data to produce the CDR output.
The CDR jitter specifications
listed in this data sheet assume
an input that has been 8B/10B
encoded.
SD OUTPUT
Unused outputs should not be
left unconnected. Ideally, unused
outputs should have their differ-
ential pins shorted together with
a short PCB trace. If transmission
lines are connected to the output
pins, the lines should be differen-
tially terminated with an appro-
priate resistor. The value of the
termination resistor should
match the PCB trace differential
impedance.
EQU INPUT
The Signal Detect (SD) block
detects if the incoming data on
FM_NODE[0]± is valid by exam-
ining the differential amplitude of
that input. The incoming data is
considered valid, and SD is driven
high, as long as the amplitude is
greater than 400 mV (differential
peak-to-peak). SD is driven low
as long as the amplitude of the
input signal is less than 100 mV
(differential peak-to-peak). When
the amplitude of the input signal
is between 100-400 mV (differen-
tial peak-to-peak), SD is
unpredictable.
BLL OUTPUT
All FM_NODE[n]± high-speed
differential inputs have an Equal-
ization (EQU) buffer to offset the
effects of skin loss and dispersion
on PCBs. An external termination
resistor is required across all
high-speed inputs.
BYPASS[N]– INPUT
The Clock and Data Recovery
(CDR) block is responsible for
frequency and phase locking onto
the incoming serial data stream
and resampling the incoming data
based on the recovered clock. An
automatic locking feature allows
the CDR to lock onto the input
data stream without external
All TO_NODE[n]± high-speed
differential outputs are driven by
a Buffered Line Logic (BLL) cir-
cuit that has on-chip source ter-
mination, so no external bias
resistors are required. The BLL
Outputs on the HDMP-0452 are
of equal strength and can drive in
excess of 120 inches of FR-4 PCB
trace.
The active low BYPASS[n]–
inputs control the data flow
through the HDMP-0452. All
BYPASS pins are LVTTL and con-
tain internal pull-up circuitry. To
bypass a port, the appropriate
BYPASS[n]– pin should be con-
nected to GND through a 1 kΩ
resistor. Otherwise, the
BYPASS[n]– inputs should be left
to float. In this case, the internal
pull-up circuitry will force them
high.
REFCLK INPUT
The LVTTL REFCLK input pro-
vides a reference oscillator for
frequency acquisition of the CDR.
The REFCLK frequency should be
within
±
100 ppm of one-tenth of
the incoming data rate in baud
(106.25 MHz
±
100 ppm for
FC-AL running at 1.0625 GBd).
2
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