FM_NODE[2]+
FM_NODE[3]+
FM_NODE[2]–
44 43 42 41 40 39 38 37 36 35 34
GND
V
CC
FM_NODE [1]–
FM_NODE [1]+
V
CC
HS[1]
TO_NODE [1]–
TO_NODE [1]+
GND
FM_NODE [0]–
FM_NODE [0]+
GND
1
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17 18 19 20 21 22
33
32
31
GND
V
CC
A
TO_NODE[4]+
TO_NODE[4]–
V
CC
HS[4]
FM_NODE[4]+
FM_NODE[4]–
V
CC
HS[0]
TO_NODE[0]–
TO_NODE[0]+
GND
GND
FM_NODE[3]–
TO_NODE[2]+
TO_NODE[3]+
TO_NODE[2]–
TO_NODE[3]–
V
CC
HS[2]
V
CC
HS[3]
Agilent
HDMP-0452
nnnn-nnn Rz.zz
S YYWW
30
29
28
27
26
25
24
23
BYPASS[0]–
BYPASS[1]–
BYPASS[2]–
BYPASS[3]–
BYPASS[4]–
REFCLK
CPLL1
GND
SD
nnnn-nnn
= WAFER LOT – BUILD NUMBER
Rz.zz
= DIE REVISION
S
= SUPPLIER CODE
YYWW
= DATE CODE (YY = YEAR,
WW
= WORK WEEK)
COUNTRY
= COUNTRY OF MANUFACTURE
(ON BACK SIDE)
Figure 2. HDMP-0452 package layout and marking, top view.
I/O Type Definitions
I/O Type
I-LVTTL
O-LVTTL
HS_OUT
HS_IN
C
S
Definition
LVTTL Input
LVTTL Output
High-Speed Output, LVPECL Compatible
High-Speed Input
External Circuit Node
Power Supply or Ground
4
CPLL0
V
CC
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
