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T9000 参数 Datasheet PDF下载

T9000图片预览
型号: T9000
PDF下载: 下载PDF文件 查看货源
内容描述: ISDN网络终端节点( NTN )设备 [ISDN Network Termination Node (NTN) Device]
分类和应用: 综合业务数字网
文件页数/大小: 126 页 / 1581 K
品牌: AGERE [ AGERE SYSTEMS ]
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T9000  
Preliminary Data Sheet  
November 2000  
ISDN Network Termination Node (NTN) Device  
9 HDLC with FIFO Module (continued)  
9.5 HDLC Register Set (continued)  
Table 65. HSM0: HDLC SAPI Match Pattern 0 (0x22)  
Reg  
R/W  
Bit 7  
SAPI05  
BAP7  
Bit 6  
SAPI04  
BAP6  
Bit 5  
SAPI03  
BAP5  
Bit 4  
SAPI02  
BAP4  
Bit 3  
SAPI01  
BAP3  
Bit 2  
SAPI00  
BAP2  
Bit 1  
C/R0  
BAP1  
Bit 0  
EA00  
BAP0  
HSM0  
R/W  
RESET Default  
Bit #  
Symbol  
Name/Description  
7—2  
SAPI0[5:0]  
Match Pattern 0 for SAPI. When in the HDLC mode, this register provides the match  
pattern for SAPI. See Section 9.4, Address Recognition for details.  
BAP[7:2]  
Byte Alignment Pattern. When in transparent mode, this register provides the byte  
alignment pattern if HRCF[BAE] = 1.  
1
0
C/R0  
Command/Response Bit. Set according to the Q.920 standard.  
BAP1  
Byte Alignment Pattern. When in transparent mode, this register provides the byte  
alignment pattern if HRCF[BAE] = 1.  
EA00  
BAP0  
Address Field Extension Bit (0 or 1). This bit has to be 0 for recognizing SAPI0 and  
SAPI63 addresses.  
Byte Alignment Pattern. When in transparent mode, this register provides the byte  
alignment pattern if HRCF[BAE] = 1.  
Table 66. HTM0: HDLC TEI Match Pattern 0 (0x23)  
Reg  
R/W  
Bit 7  
TEI06  
Bit 6  
TEI05  
Bit 5  
TEI04  
Bit 4  
TEI03  
Bit 3  
TEI02  
Bit 2  
TEI01  
Bit 1  
TEI00  
Bit 0  
EA10  
HTM0  
R/W  
RESET Default  
Bit #  
Symbol  
Name/Description  
7—1 TEI0[6:0] Match Pattern 0 for TEI. See Section 9.4, Address Recognition for details.  
0
EA10  
Address Field Extension Bit (0 or 1). This bit has to be 1 for recognizing the special TEI127  
value of 127.  
Table 67. HSM1: HDLC SAPI Match Pattern 1 (0x24)  
Reg  
R/W  
Bit 7  
SAPI15  
Bit 6  
SAPI14  
Bit 5  
SAPI13  
Bit 4  
SAPI12  
Bit 3  
SAPI11  
Bit 2  
SAPI10  
Bit 1  
C/R1  
Bit 0  
EA01  
HSM1  
R/W  
RESET Default  
Bit #  
Symbol  
Name/Description  
7—2 SAPI1[5:0] Match Pattern 1 for SAPI. When in the HDLC mode, this register provides the match pat-  
tern for SAPI. See Section 9.4, Address Recognition for details.  
1
0
C/R1  
EA01  
Command/Response Bit. Set according to the Q.920 standard.  
Address Field Extension Bit (0 or 1). This bit has to be 0 for recognizing SAPI0 and  
SAPI63 addresses.  
Lucent Technologies Inc.  
63  
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