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T9000 参数 Datasheet PDF下载

T9000图片预览
型号: T9000
PDF下载: 下载PDF文件 查看货源
内容描述: ISDN网络终端节点( NTN )设备 [ISDN Network Termination Node (NTN) Device]
分类和应用: 综合业务数字网
文件页数/大小: 126 页 / 1581 K
品牌: AGERE [ AGERE SYSTEMS ]
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T9000  
Preliminary Data Sheet  
November 2000  
ISDN Network Termination Node (NTN) Device  
9 HDLC with FIFO Module (continued)  
9.5 HDLC Register Set (continued)  
Table 57. HTTH: HDLC Transmit FIFO Threshold (0x1A)  
Reg  
R/W  
Bit 7  
P_CLASS  
1
Bit 6  
Bit 5  
TFAE5  
1
Bit 4  
TFAE4  
0
Bit 3  
TFAE3  
0
Bit 2  
TFAE2  
0
Bit 1  
TFAE1  
0
Bit 0  
TFAE0  
0
HTTH  
R/W  
RESET Default  
0
Bit #  
Symbol  
Name/Description  
7
P_CLASS Priority Class. This bit is used during arbitration to the upstream D-channel access. It indi-  
cates the number of consecutive ones the NTN has to receive on the upstream S/T D chan-  
nel in order to grant D-channel access to the HDLC transmitter.  
0: Priority class 2 (data) as defined in ITU-I.430.  
1: Priority class 1 (signaling) as defined in ITU-I.430.  
Within a class, priority levels are automatically managed.  
6
Reserved. Program to 0.  
5—0 TFAE[5:0] HDLC Transmitter FIFO Almost Empty Threshold. The HDLC transmitter will issue an  
interrupt (if enabled) when the number of empty bytes in the transmit FIFO exceeds the  
threshold level programmed in this register. The interrupt will clear when the interrupt status  
register is read. The interrupt will not be asserted again until the number of empty bytes in the  
transmit FIFO is equal to or less than the value programmed in TFAE[5:0], and then enough  
bytes are transmitted to again cause the FIFO empty level to exceed the TFAE[5:0] value.  
Table 58. HRTH: HDLC Receive FIFO Threshold (0x1B)  
Reg  
R/W  
Bit 7  
Bit 6  
Bit 5  
RFAF5  
1
Bit 4  
RFAF4  
0
Bit 3  
RFAF3  
0
Bit 2  
RFAF2  
0
Bit 1  
RFAF1  
0
Bit 0  
RFAF0  
0
HRTH  
R/W  
RESET Default  
0
0
Bit #  
7—6  
5—0  
Symbol  
Name/Description  
Reserved. Program to 0.  
HDLC Receiver FIFO Almost Full Threshold. The HDLC receiver will issue an interrupt  
(if enabled) when the number of bytes in the receive FIFO exceeds the threshold level  
programmed in this register. The interrupt will clear when the interrupt status register is  
read. The interrupt will not be asserted again until the number of bytes in the receive  
FIFO is equal to or less than the value programmed in RFAF[5:0], and enough bytes are  
received to again cause the FIFO fill level to exceed the RFAF[5:0] value.  
RFAF[5:0]  
60  
Lucent Technologies Inc.