T9000
Preliminary Data Sheet
November 2000
ISDN Network Termination Node (NTN) Device
9 HDLC with FIFO Module (continued)
9.5 HDLC Register Set (continued)
Table 75. HIR: HDLC Interrupt Register (0x2C)
Reg
R/W
Bit 7
RSTF
—
Bit 6
ROVR
—
Bit 5
REOF
—
Bit 4
RABT
—
Bit 3
RTHR
—
Bit 2
TUNDR
—
Bit 1
TFC
—
Bit 0
TTHR
—
HIR
R
RESET Default
Note: All bits in this register are set to 1 upon occurrence of the corresponding interrupt condition, and are cleared
to 0 when the register is read.
Bit #
Symbol
Name/Description
7
RSTF
Receiver Status Full Interrupt. This interrupt occurs when the receiver FIFO is filled
with 16 status bytes.
6
5
4
3
2
1
0
ROVR
REOF
RABT
RTHR
TUNDR
TFC
Receive FIFO Overrun Interrupt. This interrupt occurs when a received byte is written
to a full receive FIFO.
Receive End of Frame Interrupt. This interrupt occurs when an end of frame (EOF)
status byte is written to the receive FIFO.
Receive Abort Detect Interrupt. This interrupt occurs when the receiver detects an
abort condition.
Receive FIFO Threshold Interrupt. This interrupt occurs when the receiver almost full
threshold is exceeded.
Transmit FIFO Underrun Interrupt. This interrupt occurs when the transmitter attempts
to transmit a byte from an empty transmit FIFO.
Transmit Frame Complete Interrupt. This interrupt occurs when the transmitter has
successfully transmitted a frame.
TTHR
Transmit FIFO Threshold Interrupt. This interrupt occurs when the transmitter almost
empty threshold is exceeded.
Lucent Technologies Inc.
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