T9000
Preliminary Data Sheet
November 2000
ISDN Network Termination Node (NTN) Device
9 HDLC with FIFO Module (continued)
9.5 HDLC Register Set (continued)
Table 62. HTXL: HDLC Transmit Data Last Byte (0x1F)
Reg
R/W
Bit 7
TXDL7
—
Bit 6
TXDL6
—
Bit 5
TXDL5
—
Bit 4
TXDL4
—
Bit 3
TXDL3
—
Bit 2
TXDL2
—
Bit 1
TXDL1
—
Bit 0
TXDL0
—
HTXL
W
RESET Default
Bit #
Symbol
Name/Description
HDLC Transmit Data—Last Byte. The last data byte of each transmitted packet is writ-
ten to this register (rather than HTX) to indicate to the transmitter that this is the end of
the packet. This register occupies the same physical space as HTX (i.e., it maps to the
transmit FIFO).
7—0
TXDL[7:0]
Table 63. HRX: HDLC Receive Data (0x20)
Reg
R/W
Bit 7
RXD7
—
Bit 6
RXD6
—
Bit 5
RXD5
—
Bit 4
RXD4
—
Bit 3
RXD3
—
Bit 2
RXD2
—
Bit 1
RXD1
—
Bit 0
RXD0
—
HRX
R
RESET Default
Bit #
Symbol
Name/Description
Received Data/Status. The content of the FIFO is read when addressing this register.
The first received bit is the least significant bit of this byte.
7—0
RXD[7:0]
Table 64. HSCR: HDLC SAPI C/R Bit Mask (0x21)
Reg
R/W
Bit 7
—
Bit 6
—
Bit 5
—
Bit 4
—
Bit 3
S3CRE
0
Bit 2
S2CRE
0
Bit 1
S1CRE
0
Bit 0
S0CRE
0
HSCR
R/W
RESET Default
0
0
0
0
Bit #
7—4
3
Symbol
Name/Description
—
Reserved. Program to 0.
SAPI3 Command/Response Bit Comparison Enable.
S3CRE
S2CRE
S1CRE
S0CRE
0: SAPI3 C/R bit is ignored.
1: SAPI3 comparison includes C/R bit (HSM3.1).
SAPI2 Command/Response Bit Comparison Enable.
2
1
0
0: SAPI2 C/R bit is ignored.
1: SAPI2 comparison includes C/R bit (HSM2.1).
SAPI1 Command/Response Bit Comparison Enable.
0: SAPI1 C/R bit is ignored.
1: SAPI1 comparison includes C/R bit (HSM1.1).
SAPI0 Command/Response Bit Comparison Enable.
0: SAPI0 C/R bit is ignored.
1: SAPI0 comparison includes C/R bit (HSM0.1).
62
Lucent Technologies Inc.
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