T9000
Preliminary Data Sheet
November 2000
ISDN Network Termination Node (NTN) Device
9 HDLC with FIFO Module (continued)
9.5 HDLC Register Set (continued)
Table 56. HRCF: HDLC Receiver Configuration Register (0x19)
Reg
R/W
Bit 7
—
Bit 6
—
Bit 5
—
Bit 4
—
Bit 3
RXMODE
0
Bit 2
BAE
0
Bit 1
Bit 0
HRCF
R/W
DROPCRC RX_INIT
RESET Default
0
0
0
0
1
0
Bit #
7—4
3
Symbol
Name/Description
—
Reserved. Program to 0.
RXMODE Receiver Mode. Determines whether the receiver is in standard HDLC mode or transparent
mode. The receiver must be reinitialized after changing this bit.
0: Standard HDLC mode.
1: Transparent mode.
2
BAE
Byte Alignment Enable. This bit enables the byte alignment feature for the HDLC receiver
when operating in transparent mode. When this feature is enabled, register HSM0 (22h) pro-
vides the byte alignment pattern. The receiver must be reinitialized after changing this bit.
0: Byte alignment mechanism is disabled.
1: Byte alignment mechanism is enabled.
1
0
DROPCRC Drop Receive CRC. Controls whether the CRC bytes (last 2 bytes of an HDLC frame) are
loaded into the receive FIFO. The receiver must be reinitialized after changing this bit.
0: Load 2 CRC bytes into receive FIFO.
1: Drop CRC (CRC bytes are not loaded into the receive FIFO).
RX_INIT HDLC Receiver Initialize. Writing this bit to 1 will cause initialization of the HDLC receiver.
On powerup, the HDLC receiver is initialized automatically. After powerup, whenever there
is any change in the DROPCRC, RXMODE, BAE, or HSM0[BAP(7:0)] configuration bits, this
bit needs to be set to reinitialize the HDLC receiver. Prior to programming any of the receiver
registers, this bit must be written to 1. The microcontroller must then poll this bit and wait
until it returns to 0 (signaling that receiver initialization is complete) before programming any
of the other receiver registers. During initialization, DROPCRC is latched. Any change to
DROPCRC after initialization is disregarded.
Lucent Technologies Inc.
59
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