T9000
Preliminary Data Sheet
November 2000
ISDN Network Termination Node (NTN) Device
9 HDLC with FIFO Module (continued)
9.5 HDLC Register Set (continued)
Table 59. HTSA: HDLC Transmit FIFO Space Available (0x1C)
Reg
R/W
Bit 7
—
Bit 6
TSP6
1
Bit 5
TSP5
0
Bit 4
TSP4
0
Bit 3
TSP3
0
Bit 2
TSP2
0
Bit 1
TSP1
0
Bit 0
TSP0
0
HTSA
R
RESET Default
—
Bit #
7
Symbol
Name/Description
—
Reserved.
Transmitter Space. This register contains the number of empty positions in the transmit-
ter FIFO.
6—0
TSP[6:0]
Table 60. HRDA: HDLC Receive FIFO Data Available (0x1D)
Reg
R/W
Bit 7
SWRF
—
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HRDA
R
NBNSW6 NBNSW5 NBNSW4 NBNSW3 NBNSW2 NBNSW1 NBNSW0
RESET Default
—
—
—
—
—
—
—
Bit #
Symbol
Name/Description
Status Word on Receive FIFO. The HDLC receiver module asserts this bit whenever
there is a status word in the receive FIFO.
7
SWRF
0: No status word.
1: Status word.
Number of Bytes Until Next Status Word. These bits indicate how many bytes are
present in the receive FIFO. If SWRF (bit 7) is equal to 1, indicating that a status word is
available in the FIFO, then NBNSW[6:0] indicates the number of bytes in the receive
FIFO up to and including the status byte. If SWRF is equal to 0, indicating that no status
words are available in the FIFO, then NBNSW[6:0] indicates the total number of data
bytes in the receive FIFO.
6—0 NBNSW[6:0]
Table 61. HTX: HDLC Transmit Data (0x1E)
Reg
R/W
Bit 7
TXD7
—
Bit 6
TXD6
—
Bit 5
TXD5
—
Bit 4
TXD4
—
Bit 3
TXD3
—
Bit 2
TXD2
—
Bit 1
TXD1
—
Bit 0
TXD0
—
HTX
W
RESET Default
Name/Description
Bit #
Symbol
HDLC Transmit Data. Data to be transmitted is written to this register, which maps into
the transmit FIFO. The last byte of each packet must be written to register HTXL (see
Table 62).
7—0
TXD[7:0]
Lucent Technologies Inc.
61
AGERE [ AGERE SYSTEMS ]
