T9000
Preliminary Data Sheet
November 2000
ISDN Network Termination Node (NTN) Device
6 Functional Modules (continued)
6.6 Interrupt Register Set (continued)
Table 13. GIR1: Global Interrupt Register 1 (0x01)
Reg
R/W
Bit 7
—
Bit 6
—
Bit 5
—
Bit 4
XI1I
0
Bit 3
HDLCI
0
Bit 2
GCII
0
Bit 1
CMPI
0
Bit 0
PWMI
0
GIR1
R
RESET Default
—
—
—
Note: All bits in this register are set to 1 upon occurrence of the corresponding interrupt condition, and remain set
until the interrupt condition causing the interrupt goes away.
Bit
Symbol
Name/Description
7—5
—
Reserved.
4
3
2
1
XI1I
HDLCI
GCII
External XINT1 Interrupt. This interrupt follows the level on the NTN external interrupt pin
XINT1.
HDLC Interrupt. This interrupt occurs when any of the interrupt bits in the HDLC interrupt
register (HIR) are active, i.e., all of the HDLC interrupts are collapsed into this bit.
GCI Interrupt. This interrupt occurs when any of the interrupt bits in the GCI interrupt
register (GCIR) are active, i.e., all of the GCI interrupts are collapsed into this bit.
CMPI
Comparator Interrupt. This interrupt occurs when any of the interrupt bits in the comparator
interrupt register (CIR) are active, i.e., all of the comparator interrupts are collapsed into this
bit.
0
PWMI
PWM Interrupt. This interrupt occurs when any of the interrupt bits in the PWM interrupt
register (PWIR) are active, i.e., all of the PWM interrupts are collapsed into this bit.
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