T9000
Preliminary Data Sheet
November 2000
ISDN Network Termination Node (NTN) Device
5 Control Register Memory Space (continued)
Table 11. Control Register Memory Space (continued)
Register Address Register Mnemonic
Description
GCI PFS1 Offset Select
Refer To
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
GCOF1
GCOF2
GCDMD
GCDML
GCUMD
GCDCI
GCUCI
GCIR
Table 81 on page 80
Table 82 on page 80
Table 83 on page 81
Table 84 on page 81
Table 85 on page 81
Table 86 on page 82
Table 87 on page 82
Table 88 on page 83
Table 89 on page 84
Table 90 on page 86
Table 91 on page 87
Table 92 on page 87
Table 93 on page 88
Table 94 on page 89
Table 95 on page 89
Table 96 on page 90
Table 97 on page 90
Table 98 on page 90
Table 99 on page 91
Table 100 on page 91
Table 101 on page 92
Table 104 on page 100
GCI PFS2 Offset Select
GCI Downstream (Transmit) Monitor Data
GCI Downstream (Transmit) Monitor Data Last
GCI Upstream (Receive) Monitor Data
GCI Downstream (Transmit) C/I Data
GCI Upstream (Receive) C/I Data
GCI Interrupt Register
GCIE
GCI Interrupt Enable
GPDIR0
GPDIR1
GPDIR2
GPAF0
GPAF1
GPD0
GPIO Port 0 Pin Direction
GPIO Port 1 Pin Direction
GPIO Port 2 Pin Direction
GPIO Alternate Function Register #0
GPIO Alternate Function Register #1
GPIO Port 0 Data Register
GPD1
GPIO Port 1 Data Register
GPD2
GPIO Port 2 Data Register
GPLEI
GPIO Level-Edge-Triggered Interrupt Control
GPIO Interrupt Polarity Control
GPIO Interrupt Register
GPPOL
GPIR
GPIE
GPIO Interrupt Enable
PW0CF
PW0VH
PW0VL
PW1CF
PW1VH
PW1VL
PWIR
Pulse-Width Modulator 0 Configuration
Pulse-Width Modulator 0 Pulse-Width Value, High Byte
Pulse-Width Modulator 0 Pulse-Width Value, Low Byte
Pulse-Width Modulator 1 Configuration
Pulse-Width Modulator 1 Pulse-Width Value, High Byte
Pulse-Width Modulator 1 Pulse-Width Value, Low Byte
Pulse-Width Modulator Interrupt Register
dc/dc Configuration Register
Table 105 on page 101
Table 106 on page 101
Table 107 on page 102
Table 108 on page 103
Table 109 on page 103
Table 110 on page 103
Table 111 on page 104
Table 113 on page 106
Table 114 on page 106
Table 115 on page 107
Table 116 on page 107
Table 41 on page 47
Table 42 on page 47
Table 43 on page 48
Table 44 on page 48
Table 45 on page 48
Table 46 on page 49
Table 47 on page 49
Table 48 on page 49
Table 49 on page 50
Table 50 on page 50
Table 51 on page 50
Table 52 on page 50
Table 53 on page 51
Table 54 on page 51
DCCF
CME
Comparator Enable
CMT
Comparator Transition Polarity
CMIR
Comparator Interrupt Register
CMIE
Comparator Interrupt Enable
DOCR
Device Operation Control Register
B1UP
B1-Channel Upstream Data from GCI to U-Interface
B2-Channel Upstream Data from GCI to U-Interface
B1-Channel Downstream Data from GCI to U-Interface
B2-Channel Downstream Data from GCI to U-Interface
Reserved Register for Internal Use
B2UP
B1DN
B2DN
Reserved1
Reserved2
Reserved3
Reserved4
Reserved5
Reserved6
Reserved7
Reserved8
Reserved9
16
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