T9000
Preliminary Data Sheet
November 2000
ISDN Network Termination Node (NTN) Device
6 Functional Modules (continued)
6.5 Interrupts (continued)
External pins XINT0 and XINT1 are also collapsed in the UCI module. XINT0 is collapsed into register GIR0 in bit
XI0I. XINT1 is collapsed into register GIR1 in bit XI1I. These interrupts are maskable via the corresponding inter-
rupt enable bits (see register GIE).
NTN OFF-CHIP RAM
(80C32 EXTERNAL SPACE)
FFFFh
(64K)
UP TO 60K
ACCESSIBLE
EXTERNAL
NTN ON-CHIP RAM
80C32
MEMORY
(80C32 EXTERNAL SPACE)
INTERNAL RAM
0FFFh
(4K)
0FFFh
(4K)
FFh
FFh
80h
ACCESSIBLE
ACCESSIBLE
BY INDIRECT
ADDRESSING
ONLY
UPPER
128
BY DIRECT
ADDRESSING
ONLY
NTN
ON-CHIP
SRAM
LOWEST 4K
NOT
ACCESSIBLE
80h
7Fh
5Dh
ACCESSIBLE
BY DIRECT
AND
INDIRECT
ADDRESSING
SPECIAL
FUNCTION
REGISTERS
LOWER
128
NTN
DEVICE
REGISTERS
0
0
0
RDi
RD
PORTS,
ON-CHIP
EXTERNAL
QUALIFIER
STATUS AND CONTROL BITS,
TIMER, REGISTERS,
WRi
WR
STACK POINTER, ACCUMULATOR
5-6710F.a
Figure 3. NTN Data Memory Address Space
6.6 Interrupt Register Set
Table 12. GIR0: Global Interrupt Register 0 (0x00)
Reg
R/W
Bit 7
—
Bit 6
—
Bit 5
—
Bit 4
XI0I
0
Bit 3
125I
0
Bit 2
UII
0
Bit 1
SII
0
Bit 0
GIR0
R
GPIOI
0
RESET Default
—
—
—
Note: All bits in this register are set to 1 upon occurrence of the corresponding interrupt condition, and remain set
until the interrupt condition causing the interrupt goes away.
Bit
Symbol
Name/Description
7—5
—
Reserved.
4
3
2
1
0
XI0I
125I
UII
External XINT0 Interrupt. This interrupt follows the level on the NTN external interrupt pin
XINT0.
125 µs Interrupt. This interrupt occurs every 125 µs. This can be used to program the timing
of the microcontroller to access the B-channel data.
U-Interface Interrupt. This interrupt occurs when any of the interrupt bits in the U interrupt
register (UIR) are active, i.e., all of the U-interface interrupts are collapsed into this bit.
SII
S-Interface Interrupt. This interrupt occurs when any of the interrupt bits in the S interrupt
register (SIR) are active, i.e., all of the S-interface interrupts are collapsed into this bit.
GPIOI
GPIO Interrupt. This interrupt occurs when any of the interrupt bits in the GPIO interrupt
register (GPIR) are active, i.e., all of the GPIO interrupts are collapsed into this bit.
18
Lucent Technologies Inc.
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