T9000
Preliminary Data Sheet
November 2000
ISDN Network Termination Node (NTN) Device
5 Control Register Memory Space
Table 11. Control Register Memory Space
Register Address Register Mnemonic
Description
Global Interrupt Register 0
Refer To
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
GIR0
GIR1
GIE
Table 12 on page 18
Table 13 on page 19
Table 14 on page 20
Table 15 on page 21
Table 16 on page 22
Table 22 on page 33
Table 23 on page 34
Table 24 on page 35
Table 25 on page 36
Table 26 on page 37
Table 27 on page 37
Table 28 on page 38
Table 29 on page 39
Table 30 on page 39
Table 31 on page 39
Table 32 on page 40
Table 33 on page 41
Table 34 on page 42
Table 35 on page 43
Table 36 on page 43
Table 37 on page 44
Table 38 on page 45
Table 39 on page 46
Table 40 on page 46
Table 55 on page 58
Table 56 on page 59
Table 57 on page 60
Table 58 on page 60
Table 59 on page 61
Table 60 on page 61
Table 61 on page 61
Table 62 on page 62
Table 63 on page 62
Table 64 on page 62
Table 65 on page 63
Table 66 on page 63
Table 67 on page 63
Table 68 on page 64
Table 69 on page 64
Table 70 on page 64
Table 71 on page 64
Table 72 on page 65
Table 73 on page 65
Table 74 on page 66
Table 75 on page 67
Table 76 on page 68
Table 80 on page 79
Global Interrupt Register 1
Global Interrupt Enable Register
Microcontroller Clock Control Register
Microcontroller Watchdog Timer Control
DFAC Configuration Register
Data Flow Register
UPCK
WDT
DFCF
DFR
UCR0
UCR1
USR0
USR1
ECR0
ECR1
ESR0
ESR1
SCR0
SCR1
SSR
U-Interface Control Register #0
U-Interface Control Register #1
U-Interface Status Register #0
U-Interface Status Register #1
EOC Control Register 0—Command and Address
EOC Control Register 1—Message
EOC Status Register 0—Command and Address
EOC Status Register 1—Message
S-Interface Control Register #0
S-Interface Control Register #1
S-Interface Status Register
MFR0
MFR1
UIR
Multiframe Register, Q-Channel Data
Multiframe Register, S-Subchannel Data
U-Interface Interrupt Register
U-Interface Enable Register
UIE
SIR
S-Interface Interrupt Register
S-Interface Enable Register
SIE
HTCF
HRCF
HTTH
HRTH
HTSA
HRDA
HTX
HDLC Transmitter Configuration Register
HDLC Receiver Configuration Register
HDLC Transmit FIFO Threshold
HDLC Receive FIFO Threshold
HDLC Transmit FIFO Space Available
HDLC Receive FIFO Data Available
HDLC Transmit Data
HTXL
HRX
HDLC Transmit Data Last Byte
HDLC Receive Data
HSCR
HSM0
HTM0
HSM1
HTM1
HSM2
HTM2
HSM3
HTM3
HSMOD
HTMOD
HIR
HDLC SAPI C/R Bit Mask
HDLC SAPI Match Pattern 0
HDLC TEI Match Pattern 0
HDLC SAPI Match Pattern 1
HDLC TEI Match Pattern 1
HDLC SAPI Match Pattern 2
HDLC TEI Match Pattern 2
HDLC SAPI Match Pattern 3
HDLC TEI Match Pattern 3
HDLC SAPI Modifier Register
HDLC TEI Modifier Register
HDLC Interrupt Register
HIE
HDLC Interrupt Enable 15
GCCF
GCI+ Configuration Register
Lucent Technologies Inc.
15
AGERE [ AGERE SYSTEMS ]
