T9000
Preliminary Data Sheet
November 2000
ISDN Network Termination Node (NTN) Device
ONCE mode. In normal operation, XINT0 and XINT1
pins on the NTN are inputs with internal pull-ups
(thus an external open-drain driver does not require
a pull-up). In ONCE mode, the XINT0 and XINT1
pins become open-drain outputs (with internal pull-
ups) so that the NTN can drive the internal status of
the XINT0 and XINT1 signals onto the corresponding
emulator pins. Note that this means that, in ONCE
mode, the interrupt service routine (ISR) for INT0
and INT1 will need to be modified to reflect this differ-
ence. This is because in normal mode, the microcon-
troller will see X|0| or X|1| go high in registers GR0
and GR1, respectively, when an external interrupt
occurs. However, in ONCE mode, the occurrence of
an external interrupt will change the level on the
emulator’s INT0 and INT1 pins, but this change will
not show up in the X|0| or X|1| interrupt bits in the
NTN. Therefore, the ISR will need to assume that, if
no bits in GIR0 (for an XINT0 interrupt) or GIR1 (for
an XINT1 interrupt) are set and an interrupt has
occurred, then the ISR for the corresponding exter-
nal interrupt should be invoked.
6 Functional Modules (continued)
6.9 On-Circuit Emulation (ONCE) Mode
The external access port pin SLP is used to put the
device under the control of an external microcontroller.
The ONCE mode is invoked by the following two steps:
■ Pulling SLP and RESET low.
■ Holding SLP low while releasing RESET.
Table 5 lists the functions of the microcontroller’s exter-
nal access pins during ONCE mode.
6.10 Emulation
When using ONCE mode, some special provisions
must be made on the target system to ensure accurate
emulation as follows:
■ If the target system’s NTN uses external RAM, a
memory decoder must be added to the board to sup-
port emulation. This decoder must select the external
RAM only during accesses to addresses above the
lowest 4K of memory. This is not necessary during
normal operation because the NTN disables the RD
and WR strobes that are routed to the external mem-
ory whenever an access is being made to the inter-
nal 4K of RAM. However, during emulation mode,
the signals are being driven by the external emulator
and will be presented to the external RAM for all
external data accesses, including the lowest 4K. This
will create contention between the internal 4K of
RAM and the lowest 4K of external RAM. As a simple
example of required decoding logic, if using an exter-
nal 4K RAM, the A12 address line could be inverted
and used to drive the RAM’s CS signal. For an exter-
nal 8K RAM, the NOR of the A12 and A13 lines could
be used to drive CS. For an external 16K RAM, the
NOR of A12 through A14 could be used to drive CS,
etc. This logic is not required when using the system
in normal (nonemulation) mode.
6.11 Module I/O
The I/O interface for this module is identical to that doc-
umented in the Lucent 80C31/32/51/52 data sheet,
with the exception of the ALE signal. ALE is also
an input to the 80C32 block. This is required to allow
an external microcontroller to access the internal
4 Kbytes address space during ONCE mode.
During ONCE mode, there is a direct connection
between the external access port signals and their
associated signals on the microcontroller interface. For
this purpose, a shell was created around the original
block. This shell is essentially a set of multiplexers that,
during ONCE mode, allows the external port access
signals to drive the XDBALE, XDBTI, IOLAD, IOHAD,
WR, and RD signals on the internal microcontroller
interface.
■ If any of the GPIO1.[7:5] pins are being used as
inputs to trigger internal timers T2, T1, and T0 (see
register GPAF1), these signals must also be routed
to the 80C32 emulator’s port pins P1.0, P3.5, and
P3.4, respectively, in order to trigger the correspond-
ing timers on the emulator.
■ External interrupt sources that normally drive XINT0
and XINT1 should be open-drain drivers to avoid
contention with the XINT0 and XINT1 pins during
Lucent Technologies Inc.
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