Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
.
Table 61 Master Serial Configuration Mode Timing Characteristics
<
<
<
<
T +85 °C.
DD
A
DD
A
OR3Cxx Commercial: V
= 5.0 V ± 5%, 0 °C
= 3.0 V to 3.6 V, 0 °C
T
70 °C; Industrial: V
= 5.0 V ± 10%, –40 °C
DD
<
<
<
<
T +85 °C.
DD
A
A
OR3Txxx Commercial: V
T
70 °C; Industrial: V
= 3.0 V to 3.6 V, –40 °C
Parameter
DIN Setup Time*
Symbol
Min
60.00
0.00
5.00
0.63
—
Max
—
Unit
ns
S
T
H
T
C
F
C
F
D
T
DIN Hold Time
—
ns
CCLK Frequency (M3 = 0)
CCLK Frequency (M3 = 1)
CCLK to DOUT Delay
16.67
2.08
5.00
MHz
MHz
ns
* Data gets clocked out from an external serial ROM. The clock to data delay of the serial ROM must be less than the CCLK frequency since
the data available out of the serial ROM must be setup and waiting to be clocked into the FPGA before the next CCLK rising edge.
Note: Serial configuration data is transmitted out on DOUT on the falling edge of CCLK after it is input on DIN.
CCLK
TS
TH
BIT N
DIN
TD
DOUT
BIT N
5-4532(F)
Figure 83. Master Serial Configuration Mode Timing Diagram
136
Lucent Technologies Inc.
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