Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Table 65. Slave Parallel Configuration Mode Timing Characteristics
<
<
<
<
T +85 °C.
DD
A
DD
A
OR3Cxx Commercial: V
= 5.0 V ± 5%, 0 °C
= 3.0 V to 3.6 V, 0 °C
T
70 °C; Industrial: V
= 5.0 V ± 10%, –40 °C
DD
<
<
<
<
T +85 °C.
DD
A
A
OR3Txxx Commercial: V
T
70 °C; Industrial: V
= 3.0 V to 3.6 V, –40 °C
Parameter
CS0, CS1, WR Setup Time
CS0, CS1, WR Hold Time
Symbol
Min
Max
—
Unit
ns
S1
T
H1
T
S2
T
40.00
20.00
—
ns
D[7:0] Setup Time:
3Cxx
3Txxx
20.00
7.00
—
—
ns
ns
H2
D[7:0] Hold Time
T
0.00
—
ns
CH
T
CCLK High Time:
3Cxx
20.00
7.00
—
—
ns
ns
3Txxx
CL
CCLK Low Time:
3Cxx
T
20.00
7.00
—
—
ns
ns
3Txxx
C
F
CCLK Frequency:
3Cxx
—
—
25.00
66.00
MHz
MHz
3Txxx
Note: Daisy-chaining of FPGAs is not supported in this mode.
CS0
CS1
WR
TS1
TH1
TCH
TCL
CCLK
TH2
TS2
D[7:0]
5-2848(F)
Figure 87. Slave Parallel Configuration Mode Timing Diagram
140
Lucent Technologies Inc.
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