Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Table 59. OR3C/Txxx Input to General System Clock (SCLK) Setup/Hold Time (Pin-to-Pin)
DD
<
A
<
DD
<
A
<
OR3Cxx Commercial: V = 5.0 V ± 5%, 0 °C
T
70 °C; Industrial: V = 5.0 V ± 10%, –40 °C
T +85 °C.
DD
<
A
<
DD
<
A
<
OR3Txxx Commercial: V = 3.0 V to 3.6 V, 0 °C
T
70 °C; Industrial: V = 3.0 V to 3.6 V, –40 °C
T +85 °C.
Speed
Description
Device
Unit
Max
-4
-5
-6
-7
J
DD
(T = 85 °C, V = min)
Min
Max
Min
Max
Min
Max
Min
Input to SCLK Setup Time
ns
ns
ns
ns
ns
OR3T20
OR3T30
OR3C/T55
OR3C/T80
OR3T125
—
—
0.00
0.00
—
—
—
—
—
—
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
Input to SCLK Setup Time
(delayed data input)
ns
ns
ns
ns
ns
OR3T20
OR3T30
OR3C/T55
OR3C/T80
OR3T125
—
—
0.99
0.79
—
—
—
—
—
—
1.33
1.22
1.09
0.93
0.78
—
—
—
—
—
1.47
1.40
1.33
1.26
1.19
—
—
—
—
—
3.09
3.03
2.97
2.91
2.86
—
—
—
—
—
Input to SCLK Hold Time
ns
ns
ns
ns
ns
OR3T20
OR3T30
OR3C/T55
OR3C/T80
OR3T125
—
—
6.82
7.62
—
—
—
—
—
—
4.74
5.01
5.56
6.19
7.07
—
—
—
—
—
3.64
3.83
4.18
4.56
5.14
—
—
—
—
—
3.04
3.22
3.54
3.89
4.44
—
—
—
—
—
Input to SCLK Hold Time
(delayed data input)
ns
ns
ns
ns
ns
OR3T20
OR3T30
OR3C/T55
OR3C/T80
OR3T125
—
—
0.00
0.00
—
—
—
—
—
—
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
Additional Hold Time if Non-
mid-PIC Used as SCLK Pin
(no delay on data input)
ns
ns
ns
ns
ns
OR3T20
OR3T30
OR3C/T55
OR3C/T80
OR3T125
—
—
0.41
0.63
—
—
—
—
—
—
0.16
0.20
0.36
0.55
1.11
—
—
—
—
—
0.18
0.21
0.37
0.57
1.05
—
—
—
—
—
0.17
0.20
0.35
0.55
1.02
—
—
—
—
—
Notes:
ORCA
The pin-to-pin timing parameters in this table should be used instead of results reported by
Foundry.
This clock delay is for a fully routed clock tree that uses the clock network. It includes both the input buffer delay and the clock routing to the PIO
FF CLK input. The delay will be reduced if any of the clock branches are not used. The given setup (delayed and no delay) and hold (delayed)
timing allows the input clock pin to be located in any PIO on any side of the device, but a PIO FF must be used. The hold (no delay) timing
assumes the clock pin is located at one of the four middle PICs on any side of the device and that a PIO FF is used. If the clock pin is located
elsewhere, then the last parameter in the table must be added to the hold (no delay) timing.
PIO FF
INPUT
SCLK
D
Q
5-4847(F)
Figure 81. Input to System Clock Setup/Hold Time
132
Lucent Technologies Inc.
AGERE [ AGERE SYSTEMS ]
