Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
.
Table 63 Asynchronous Peripheral Configuration Mode Timing Characteristics
<
<
<
<
T +85 °C.
DD
A
DD
A
OR3Cxx Commercial: V
= 5.0 V ± 5%, 0 °C
= 3.0 V to 3.6 V, 0 °C
T
70 °C; Industrial: V
= 5.0 V ± 10%, –40 °C
DD
<
<
<
<
T +85 °C.
DD
A
A
OR3Txxx Commercial: V
T
70 °C; Industrial: V
= 3.0 V to 3.6 V, –40 °C
Parameter
Symbol
Min
Max
Unit
WR
T
WR, CS0, and CS1 Pulse Width
50.00
—
ns
S
D[7:0] Setup Time:
3Cxx
T
20.00
10.50
—
—
ns
ns
3Txxx
H
D[7:0] Hold Time
T
0.00
—
—
ns
ns
RDY
RDY Delay
T
40.00
8.00
—
B
RDY Low
T
1.00
0.00
—
CCLK Periods
WR2
Earliest WR After RDY Goes High*
RD to D7 Enable/Disable
CCLK to DOUT
T
ns
ns
ns
DEN
T
40.00
5.00
D
T
—
* This parameter is valid whether the end of not RDY is determined from the RDY pin or from the D7 pin.
Notes:
Serial data is transmitted out on DOUT on the falling edge of CCLK after the byte is input on D[7:0].
D[6:0] timing is the same as the write data portion of the D7 waveform because D[6:0] are not enabled by RD.
CS0
CS1
TWR
WR
TS
TH
TWR2
D7
WRITE DATA
TDEN
TDEN
RD
RDY
TB
TRDY
CCLK
DOUT
TD
D0
D1
D2
PREVIOUS BYTE
D3
D7
5-4533(F)
Figure 85. Asynchronous Peripheral Configuration Mode Timing Diagram
Lucent Technologies Inc.
138
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