Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
.
Table 62 Master Parallel Configuration Mode Timing Characteristics
<
<
<
<
DD
A
DD
A
T
OR3Cxx Commercial: V
= 5.0 V ± 5%, 0 °C
= 3.0 V to 3.6 V, 0 °C
T
70 °C; Industrial: V
= 5.0 V ± 10%, –40 °C
DD
+85 °C.
<
<
<
<
DD
A
A
T
OR3Txxx Commercial: V
T
70 °C; Industrial: V
= 3.0 V to 3.6 V, –40 °C
+85 °C.
Parameter
Symbol
Min
Max
60.00
—
Unit
ns
AV
T
RCLK to Address Valid
—
S
H
D[7:0] Setup Time to RCLK High
D[7:0] Hold Time to RCLK High
RCLK Low Time (M3 = 0)
RCLK High Time (M3 = 0)
RCLK Low Time (M3 = 1)
RCLK High Time (M3 = 1)
CCLK to DOUT
T
60.00
0.00
7.00
1.00
7.00
1.00
—
ns
T
—
ns
CL
T
7.00
1.00
7.00
1.00
5.00
CCLK cycles
CCLK cycles
CCLK cycles
CCLK cycles
ns
CH
T
CL
CH
T
T
D
T
Notes:
The RCLK period consists of seven CCLKs for RCLK low and one CCLK for RCLK high.
Serial data is transmitted out on DOUT 1.5 CCLK cycles after the byte is input on D[7:0].
A[17:0]
TAV
TCH
TCL
RCLK
TS
BYTE N
TH
D[7:0]
CCLK
BYTE N + 1
DOUT
D0
D1
D2
D3
D4
D5
D6 D7
TD
5-6764(F)
Figure 84. Master Parallel Configuration Mode Timing Diagram
Lucent Technologies Inc.
137
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