Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Configuration Timing
Table 60. General Configuration Mode Timing Characteristics
DD = 5.0 V ± 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V ± 10%, –40 °C < TA < +85 °C.
OR3Cxx Commercial: V
OR3Txxx Commercial: V
<
<
<
<
A
T
DD
A
T
DD
= 3.0 V to 3.6 V, 0 °C
70 °C; Industrial: V
= 3.0 V to 3.6 V, –40 °C
+85 °C.
Parameter
All Configuration Modes
Symbol
Min
Max
Unit
M[3:0] Setup Time to INIT High
M[3:0] Hold Time from INIT High
TSMODE
THMODE
TRW
0.00
—
—
—
—
ns
ns
ns
ns
600.00
50.00
50.00
RESET Pulse Width Low to Start Reconfiguration
PRGM Pulse Width Low to Start Reconfiguration
Master and Asynchronous Peripheral Modes
TPGW
Power-on Reset Delay
TPO
15.70
60.00
52.40
200.00
1600.00
ms
ns
ns
CCLK Period (M3 = 0)
(M3 = 1)
TCCLK
480.00
Configuration Latency (autoincrement mode):
TCL
OR3T20
(M3 = 0)
(M3 = 1)
(M3 = 0)
(M3 = 1)
(M3 = 0)
(M3 = 1)
(M3 = 0)
(M3 = 1)
(M3 = 0)
(M3 = 1)
11.50
92.10
15.10
121.00
23.20
185.00
33.70
270.00
52.30
418.00
38.40*
307.00*
50.40*
403.30*
77.40*
619.00*
113.00*
900.00*
175.00*
1395.00*
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
OR3T30
OR3C/T55
OR3C/T80
OR3T125
Microprocessor (MPI) Mode
Power-on Reset Delay
TPO
TCL
15.70
52.40
ms
Configuration Latency (autoincrement mode):
OR3T20
OR3T30
OR3C/T55
OR3C/T80
OR3T125
27413
35445
53341
76317
116581
—
—
—
—
—
write cycles
write cycles
write cycles
write cycles
write cycles
Partial Reconfiguration (explicit mode):
TPR
OR3T20
32
36
43
51
62
—
—
—
—
—
write cycles
write cycles
write cycles
write cycles
write cycles
OR3T30
OR3C/T55
OR3C/T80
OR3T125
Slave Serial Mode
Power-on Reset Delay
TPO
3.90
13.10
ms
CCLK Period
TCCLK
OR3Cxx
OR3Txxx
40
15
—
—
ns
ns
Configuration Latency (autoincrement mode):
TCL
OR3T20
OR3T30
OR3C55
OR3T55
OR3C80
OR3T80
OR3T125
2.80
3.80
—
—
—
—
—
—
—
ms
ms
ms
ms
ms
ms
ms
15.50
5.80
22.50
8.40
13.09
* Not applicable to asynchronous peripheral mode.
Lucent Technologies Inc.
133
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