LU6612
Data Sheet
July 2000
FASTCAT Single-FET for 10Base-T/100Base-TX
MII Station Management (continued)
Register Overview
The MII management 16-bit register (MR) set is implemented as described in Table 8 below.
Table 8. MII Management Registers (MR)
Register
Default
(Hex Code)
Symbol
Name
Address
0
1
MR0
MR1
MR2
MR3
MR4
MR5
MR5
MR6
MR7
Control Register
3000
7849
0180
7641
01E1
0000
—
Status Register
2
PHY Identifier Register 1
PHY Identifier Register 2
3
4
Autonegotiation Advertisement Register
5
Autonegotiation Link Partner Ability Register (Base_Page)
Autonegotiation Link Partner Ability Register (Next_Page)
Autonegotiation Expansion Register
5
6
0000
0000
0000
0000
1000
0000
7
Next-Page Transmit Register
8—27
28
29
30
MR8—MR27 Reserved
MR28
MR29
MR30
Device Specific Register 1
Device Specific Register 2
Device Specific Register 3
14
Lucent Technologies Inc.
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