Data Sheet
July 2000
LU6612
FASTCAT Single-FET for 10Base-T/100Base-TX
MII Station Management (continued)
This section provides a detailed discussion of each management register and its bit definitions.
Table 9. MR0—Control Register Bit Descriptions
Bit1
Type2
Description
0.15 (SW_RESET)
R/W
Reset. Setting this bit to a 1 will reset the LU6612. All registers will be set to
their default state. This bit is self-clearing. The default is 0.
0.14 (LOOPBACK)
0.13 (SPEED100)
0.12 (NWAY_ENA)
0.11 (PWRDN)
R/W
R/W
R/W
R/W
Loopback. When this bit is set to 1, no data transmission will take place on the
media. Any receive data will be ignored. The loopback signal path will contain
all circuitry up to, but not including, the PMD. The autonegotiation must be
turned off, before loopback can be initiated, transmit data can be started 2 ms
after loopback is initiated. The default value is a 0.
Speed Selection. The value of this bit reflects the current speed of operation
(1 = 100 Mbits/s; 0 = 10 Mbits/s). This bit will only affect operating speed when
the autonegotiation enable bit (register 0, bit 12) is disabled (0). This bit is
ignored when autonegotiation is enabled (register 0, bit 12). The bit is set high
when MODE[2:0] is 010 or 011 or 100. The default is 1.
Autonegotiation Enable. The autonegotiation process will be enabled by set-
ting this bit to a 1. This bit overrides SPEED100 bit (register 0, bit 13) and
FULL_DUP bit (register 0, bit 8). This bit is set high when MODE[2:0] is 100 or
111. Autonegotiation must be disabled before loopback can be initiated. The
default state is a 1.
Powerdown. The LU6612 may be placed in a low-power state by setting this
bit to a 1, both the 10 Mbits/s transceiver and the 100 Mbits/s transceiver will
be powered down. While in the powerdown state, the LU6612 will respond to
management transactions. The default state is a 0.
0.10 (ISOLATE)
R/W
R/W
Isolate. When this bit is set to a 1, the MII outputs will be brought to the high-
impedance state. The default state is a 0.
0.9 (REDONWAY)
Restart Autonegotiation. Normally, the autonegotiation process is started at
powerup. The process may be restarted by setting this bit to a 1. The default
state is a 0. The NWAYDONE bit (register 1, bit 5) is reset when this bit goes to
a 1. This bit is self-cleared when autonegotiation restarts.
0.8 (FULL_DUP)
R/W
Duplex Mode. This bit reflects the mode of operation (1 = full duplex; 0 = half
duplex). This bit is ignored when the autonegotiation enable bit (register 0,
bit 12) is enabled. The default state is a 0. This bit is set as a 1 during powerup/
reset, when MODE[2:0] is 001 or 011.
0.7 (COLTST)
0.6:0
R/W
NA
Collision Test. When this bit is set to a 1, the LU6612 will assert the COL sig-
nal in response to TX_EN. This bit should only be set when in loopback mode.
Reserved. All bits will read 0.
1. Note that the format for the pin descriptions is as follows: the first number is the register number, the second number is the bit position in the
register, and the name of the instantiated pad is in capital letters.
2. R = read, W = write, NA = not applicable.
Lucent Technologies Inc.
15
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